US4558434A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1984-01-25
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Granted: 1985-12-10
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Expires: 2004-01-25
Abstract
Abstract A semiconductor memory device having matrix-arranged memory cells, carrying out data write or read operations to or from a selected memory cell through a pair of data buses by the selection of a word line and a pair of bit lines, includes two transfer devices which transfer data between bit lines and data buses and which are separately operated for either writing or reading. Even if a data read operation is stopped midway by a system reset or the like, the stored data in the memory cell is not destroyed.
Inventors
- 👤 Fumio Baba
- 👤 Hirohiko Mochizuki
- 👤 Hatsuo Miyahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:23
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
119 words
A semiconductor memory device, comprising: a word line; a pair of bit lines having potentials; a memory cell operatively connected to said word line and one of said bit lines; a pair of data buses; first transfer means, operatively connected to said pair of bit lines and said pair of data buses, for transferring data from said pair of data buses to said pair of bit lines during a write operation; and second transfer means, operatively connected to said pair of bit lines and said pair of data buses, for transferring data from said pair of bit lines to said pair of data buses during a read operation without substantially changing the potentials of said pair of bit lines.
Claim 2
Dependent Claim
119 words
A semiconductor memory device, comprising: a word line; a pair of bit lines having potentials; a memory cell operatively connected to said word line and one of said bit lines; a pair of data buses; first transfer means, operatively connected to said pair of bit lines and said pair of data buses, for transferring data from said pair of data buses to said pair of bit lines during a write operation; and second transfer means, operatively connected to said pair of bit lines and said pair of data buses, for transferring data from said pair of bit lines to said pair of data buses during a read operation without substantially changing the potentials of said pair of bit lines.
Claim 3
Dependent Claim
107 words
A semiconductor memory device as set forth in claim 1, wherein each of the bit lines in said pair of bit lines has a corresponding data bus in said pair of data buses, and wherein said second transfer means comprises a first pair of transistors, each of said first pair of transistors operatively connected to the corresponding data bus for one of the bit lines in said pair of bit lines and having a gate operatively connected to the other bit line in said pair of bit lines for being controlled in response to the potential of the other bit line in said pair of bit lines.
Claim 4
Dependent Claim
63 words
A semiconductor memory device as set forth in claim 2, and operatively connectable to receive a read column selection signal, wherein said second transfer means further comprises a second pair of transistors, each of said second pair of transistors operatively connected to one of said first pair of transistors and the corresponding data bus, and connectable to receive the read column selection signal.
Claim 5
Dependent Claim
47 words
A semiconductor memory device as set forth in claim 1, further comprising: first means, operatively connected to said first transfer means, for providing a column selection signal for writing; and second means, operatively connected to said second transfer means, for providing a column selection signal for reading.
Claim 6
Dependent Claim
95 words
A semiconductor memory device as set forth in claim 4, and operatively connectable to receive a column decode signal, an inverted column decode signal and a write clock signal, wherein said first means comprises: a first transistor operatively connected to said first transfer means and connectable to receive the column decode signal and the write clock signal; a capacitor operatively connected to said first transfer means and connectable to receive the column decode signal; and a second transistor operatively connected to said first transfer means and ground, and connectable to receive the column decode signal.
Claim 7
Dependent Claim
79 words
A semiconductor memory device as set forth in claim 4, and operatively connectable to receive a column decode signal, an inverted column decode signal and a read clock signal, wherein said second means comprises: a first transistor operatively connected to said second transfer means and connectable to receive the column decode signal and the read clock signal; and a second transistor operatively connected to said second transfer means and ground, and connectable to receive the inverted column decode signal.
References Cited (Backward Citations)
US4379342A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-09 | 1989-06-10 | 1989-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-09 | 1993-06-10 | 1993-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-09 | 1997-06-10 | 1997-12-10 | $7700.00 | Window Closed / Lapsed |