Patent US4808552A successfully refreshed from Google Patents.
US4808552A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for making vertically-oriented interconnections for VLSI devices
Assignee: Texas Instruments Inc
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Filing: 1987-06-02
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Granted: 1989-02-28
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Expires: 2007-06-02
Abstract
Abstract A process is disclosed for making a conductive interconnecting path formed between two conductive areas of an integrated circuit, the conductive areas separated by at least an insulating layer of silicon nitride over a layer of oxide. The interconnecting path is formed by depositing a thick insulator coating, over the conductive and non-conductive areas then forming a vertical-walled trench, with said silicon nitride acting as an etch stop, in the thick insulator between conducting areas, then filling the trench with conductive material using chemical vapor deposition, and finally removing conductive material except for that conductive material deposited in the trench.
Inventors
- 👤 Dirk N. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:47
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/031; H10W20/056; Y; Y10; Y10S; Y10S148/00; Y10S148/02; Y10S148/043; Y10S148/114
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
195 words
A method of forming an interconnecting path between two conducting areas at a face of a semiconductor body including mutilevel oxide layers and intermediate conductor layers, said method comprising the steps of: depositing a silicon nitride layer over said multilevel oxide layers; patterning said silicon nitride layer and said multilevel oxide layers and etching holes through said silicon nitride layer and at least one of said multilevel oxide layers to expose said conductive areas; applying a thick silicon oxide layer on said face, said thick layer having a thickness greater than the width of said path; anisotropically etching said thick layer to leave a vertical-walled trench in said thick layer in the form of said path between said conductive areas and to expose said conductive areas at ends of said path, said trench having a depth determined by said silicon nitride layer acting as an etch stop; conformally depositing by chemical vapor deposition a metal layer on said face to fill said trench; removing excess metal of said metal layer from said face in areas spaced from the trench to leave sufficient metal of said metal layer in said trench to form said interconnecting path.
Claim 2
Independent Claim
195 words
A method of forming an interconnecting path between two conducting areas at a face of a semiconductor body including mutilevel oxide layers and intermediate conductor layers, said method comprising the steps of: depositing a silicon nitride layer over said multilevel oxide layers; patterning said silicon nitride layer and said multilevel oxide layers and etching holes through said silicon nitride layer and at least one of said multilevel oxide layers to expose said conductive areas; applying a thick silicon oxide layer on said face, said thick layer having a thickness greater than the width of said path; anisotropically etching said thick layer to leave a vertical-walled trench in said thick layer in the form of said path between said conductive areas and to expose said conductive areas at ends of said path, said trench having a depth determined by said silicon nitride layer acting as an etch stop; conformally depositing by chemical vapor deposition a metal layer on said face to fill said trench; removing excess metal of said metal layer from said face in areas spaced from the trench to leave sufficient metal of said metal layer in said trench to form said interconnecting path.
Claim 3
Dependent Claim
27 words
A method according to claim 1 including forming conductive plugs in said holes through said silicon nitride layer and at least one of said multilevel oxide layers.
Claim 4
Dependent Claim
16 words
A method according to claim 2, wherein the conductive plugs in said holes are of tungsten.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-28 | 1992-08-29 | 1993-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-28 | 1996-08-29 | 1997-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-28 | 2000-08-29 | 2001-02-28 | $7700.00 | Window Closed / Lapsed |