Method and circuit for digital frequency multiplication

Claim 2

A digital frequency multiplier circuit, comprising: input means for receiving a repetitive input signal; a first counter in communication with the input means to measure the period of the input signal, the first counter being clocked by a signal of frequency 1/T 1 for the duration of a predetermined portion of the input signal to develop at an output of the first counter a digital word representing the period of the input signal and during each predetermined portion of the input signal the first counter is decremented N times at the rate 1/T 1 from an initial value (M-1) to produce the digital word of value ((M-1)-N); and a second counter in communication with the first counter, the second counter receiving the digital signal to define the modulus thereof and the second counter being clocked by a signal of frequency 1/T 2 to develop at an output of the second counter a repetitive signal whose frequency is proportional to T 1 /T 2 times the frequency of the input signal.

Claim 3

The circuit of claim 1 in which the second counter comprises a binary counter having Y number of stages, the second counter developing as the repetitive output signal an overflow signal, the overflow signal undergoing a transition between logic states each time the signal of frequency 1/T 2 loads into the second counter 2 Y -((M-1)-N) number of counts.

Claim 4

The circuit of claim 2 in which the second counter comprises a presettable binary counter and the digital word of value ((M-1)-N) is programmed into the second counter to define the modulus thereof.

Claim 5

The circuit of claim 1 in which the first and second counters comprise binary counters having an equal number of stages.

Claim 6

A digital frequency multiplier circuit, comprising: input means for receiving a repetitive input signal; a first counter in communication with the input means to measure the period of the input signal, the first counter being clocked by a signal of frequency 1/T 1 for the duration of a predetermined portion of the input signal to develop at an output of the first counter a digital signal representing the period of the input signal; and a second counter in communication with the first counter, the second counter receiving the digital signal to define the modulus thereof and the second counter being clocked by a signal of frequency 1/T 2 to develop at an output of the second counter a repetitive signal whose frequency is proportional to T 1 /T 2 times the frequency of the input signal, and the signals of frequencies 1/T 1 and 1/T 2 being synchronous to each other and the input signal being asynchronous to them, and the input means including means for synchronizing the input signal to the signals of frequencies 1/T 1 and 1/T 2 prior to the communication of the input signal to the first counter.

Claim 7

A digital frequency multiplier circuit, comprising: input means for receiving a repetitive input signal; a first counter in communication with the input means to measure the period of the input signal, the first counter being clocked by a signal of frequency 1/T 1 for the duration of a predetermined portion of the input signal to develop at an output of the first counter a digital signal representing the period of the input signal; and a second counter in communication with the first counter, the second counter receiving the digital signal to define the modulus thereof and the second counter being clocked by a signal of frequency 1/T 2 to develop at an output of the second counter a repetitive signal whose frequency is proportional to T 1 /T 2 times the frequency of the input signal, and the signals of frequencies 1/T 1 and 1/T 2 being synchronous to each other and the input signal being asynchronous to them, and the input means including means for synchronizing the input signal to the signals of frequencies 1/T 1 and 1/T 2 prior to the communication of the input signal to the first counter.

Claim 8

The circuit of claim 5 in which the first and second counters comprise binary counters having an equal number of stages.

Claim 9

In a digital frequency multiplier circuit that receives a repetitive input signal of a first frequency and rapidly develops a repetitive output signal of a second frequency which is a multiple of the first frequency, a method for developing the output signal comprising the steps of: measuring the duration of a portion of the input signal by decrementing a first counter at a rate of 1/T 1 during the portion of the input signal; providing a digital remainder word at the output of the first counter whenever the first counter is initialized to its maximum value and is decremented during the portion of the input signal; programming the modulus of a second counter with the digital remainder word; and clocking the second counter at a rate of 1/T 2 to produce a repetitive output signal of a first frequency that is proportional to T 1 /T 2 times the first frequency.

Claim 10

In a digital frequency multiplier circuit that receives a repetitive input signal of a first frequency and rapidly develops a repetitive output signal of a second frequency which is a multiple of the first frequency, a method for developing the output signal comprising the steps of: measuring the duration of a portion of the input signal by decrementing a first counter at a rate of 1/T 1 during the portion of the input signal; providing a digital remainder word at the output of the first counter whenever the first counter is initialized to its maximum value and is decremented during the portion of the input signal; programming the modulus of a second counter with the digital remainder word; and clocking the second counter at a rate of 1/T 2 to produce a repetitive output signal of a first frequency that is proportional to T 1 /T 2 times the first frequency.

Claim 11

The method of claim 7 in which the first and second counters comprise digital counters of the binary type.

Claim 12

The method of claim 7 in which the portion is one cycle of the input signal.