US4144489A
Expired / Lapsed
US
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Simplified frequency to digital converter using all digital electronics
Assignee: Texas Instruments Inc
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Filing: 1974-09-23
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Granted: 1979-03-13
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Expires: 1994-09-23
Abstract
Abstract An all digital circuit converts a signal of an unknown frequency into an accurate binary representation of that frequency. The apparatus consists of an all digital closed loop system which has as its input the unknown signal. The closed loop system generates a reference signal and forces the frequency thereof to approximate that of the unknown signal. In so doing, the closed loop generates a binary number representative of the frequency of the reference signal and provides this number as the system output.
Inventors
- 👤 Phillip W. Ward
- 👤 Halbert H. Bybee, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:45
CPC Classifications
G; G01; G01R; G01R23/00; G01R23/02
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
84 words
A system for providing an accurate binary representation of the frequency of an unknown signal comprising: (a) digital phase detector means for generating a digital error signal proportional to the difference in the frequency of said unknown signal and that of a reference signal, and (b) digital closed loop means responsive to said digital error signal and operatively connected to equalize said reference signal with said unknown signal, said digital closed loop further providing a binary representation of the frequency of said reference signal.
Claim 2
Independent Claim
84 words
A system for providing an accurate binary representation of the frequency of an unknown signal comprising: (a) digital phase detector means for generating a digital error signal proportional to the difference in the frequency of said unknown signal and that of a reference signal, and (b) digital closed loop means responsive to said digital error signal and operatively connected to equalize said reference signal with said unknown signal, said digital closed loop further providing a binary representation of the frequency of said reference signal.
Claim 3
Dependent Claim
60 words
The system of claim 1 wherein said digital error signal comprises a first pulse train with a pulse repetition rate proportional to the frequency difference between said unknown and reference signals and a second binary signal the state of which is indicative of whether the frequency of said reference signal is greater or less than that of said unknown signal.
Claim 4
Independent Claim
195 words
A system for providing an accurate binary representation of the frequency of an unknown signal comprising: (a) digital phase detector means for generating a digital error signal proportional to the difference in the frequency of said unknown signal and that of a reference signal, said digital error signal comprising a first pulse train with a pulse repetition rate proportional to the frequency difference between said unknown and reference signals and a second binary signal the state of which is indicative of whether the frequency of said reference signal is greater or less than that of said unknown signal, (b) a binary counter for counting the pulses of said first pulse train wherein the count direction is controlled by the state of said second binary signal, (c) a clock for producing a second pulse train with a constant pulse repetition rate, and (d) a binary rate multiplier response to said second pulse train and to the output of said binary counter for generating said reference signal, the frequency of said reference signal being proportional to the product of the pulse repetition rate of said second pulse train and the binary number output of said binary counter.
Claim 5
Independent Claim
195 words
A system for providing an accurate binary representation of the frequency of an unknown signal comprising: (a) digital phase detector means for generating a digital error signal proportional to the difference in the frequency of said unknown signal and that of a reference signal, said digital error signal comprising a first pulse train with a pulse repetition rate proportional to the frequency difference between said unknown and reference signals and a second binary signal the state of which is indicative of whether the frequency of said reference signal is greater or less than that of said unknown signal, (b) a binary counter for counting the pulses of said first pulse train wherein the count direction is controlled by the state of said second binary signal, (c) a clock for producing a second pulse train with a constant pulse repetition rate, and (d) a binary rate multiplier response to said second pulse train and to the output of said binary counter for generating said reference signal, the frequency of said reference signal being proportional to the product of the pulse repetition rate of said second pulse train and the binary number output of said binary counter.
Claim 6
Dependent Claim
43 words
The system of claim 3 wherein said closed loop means further comprises digital divider means responsive to the reference signal output of said binary rate multiplier for reducing phase jitter in said reference signal before it is compared in said digital phase detector.
Claim 7
Dependent Claim
37 words
The system of claim 3 further comprising means for automatically setting the state of said second binary signal to make said binary counter count down whenever its output count reaches the maximum count capability of said counter.
Claim 8
Independent Claim
88 words
A system for converting the frequency of an unknown signal to a binary representation thereof, comprising: (a) digital phase detector means for generating a digital error signal representative of the frequency difference between said unknown signal and a reference signal, (b) digital integrator means for producing a multibit binary number representative of the time integral of said error signal, and (c) digital feedback loop means for generating said reference signal and for maintaining the frequency thereof proportional to the product of said multibit number and a preselected frequency.
Claim 9
Independent Claim
88 words
A system for converting the frequency of an unknown signal to a binary representation thereof, comprising: (a) digital phase detector means for generating a digital error signal representative of the frequency difference between said unknown signal and a reference signal, (b) digital integrator means for producing a multibit binary number representative of the time integral of said error signal, and (c) digital feedback loop means for generating said reference signal and for maintaining the frequency thereof proportional to the product of said multibit number and a preselected frequency.
Claim 10
Dependent Claim
68 words
The conversion system of claim 6 wherein the error signal generated by said digital phase detector means comprises a pulse train with an instantaneous pulse repetition rate proportional to the frequency difference between said unknown and reference signals and a second binary signal the state of which is indicative of whether the frequency of said reference signal is greater than or less than that of said unknown signal.
Claim 11
Dependent Claim
40 words
The conversion system of claim 7 wherein said digital integrator means comprises a binary coded decimal up/down counter and said digital feedback loop means includes a binary coded decimal binary rate multiplier responsive to the output of said up/down counter.
Claim 12
Independent Claim
87 words
A method for continuously providing an accurate binary representation of the frequency of an unknown signal comprising: (a) digitally generating an error signal representative of the frequency difference between said unknown signal and a reference signal, (b) digitally integrating said error signal to produce a multibit binary number, (c) multiplying the pulse repetition rate of a clock by said multibit binary number to produce said reference signal, and (d) linearly transforming said multibit binary number to provide a binary representation of the frequency of said unknown signal.
Claim 13
Independent Claim
87 words
A method for continuously providing an accurate binary representation of the frequency of an unknown signal comprising: (a) digitally generating an error signal representative of the frequency difference between said unknown signal and a reference signal, (b) digitally integrating said error signal to produce a multibit binary number, (c) multiplying the pulse repetition rate of a clock by said multibit binary number to produce said reference signal, and (d) linearly transforming said multibit binary number to provide a binary representation of the frequency of said unknown signal.
Claim 14
Dependent Claim
52 words
The method of claim 9 wherein said step of generating further comprises producing a first pulse train with a pulse repetition rate proportional to the frequency difference between said unknown and reference signals, and producing a second binary signal to indicate which of said unknown and reference signals has the greater frequency.
Claim 15
Dependent Claim
38 words
The method of claim 10 wherein said step of digitally integrating comprises counting the pulses of said first pulse train, the direction of counting being up or down in accordance with the state of said second binary signal.
Claim 16
Dependent Claim
40 words
The method of claim 10 further comprising the step of monitoring the short term energy level of said unknown signal and inhibiting the generation of said first pulse train when said short term energy level drops below a preselected threshold.
Claim 17
Independent Claim
173 words
A system for providing an accurate binary representation of the frequency of an unknown signal comprising: (a) digital phase detector means for generating a digital error signal proportional to the difference in the frequency of said unknown signal and that of a reference signal, said digital error signal comprising a first pulse train with a pulse repetition rate proportional to the frequency difference between said unknown and reference signals and a second binary signal the state of which is indicative of whether the frequency of said reference signal is greater or less than that of said unknown signal, (b) digital closed loop means responsive to said digital error signal and operatively connected to equalize said reference signal with said unknown signal, said digital closed loop further providing a binary representation of the frequency of said reference signal, and (c) a carrier detector for monitoring the short term average power of said unknown signal and for inhibiting the generation of said first pulse train when said average power falls below a predetermined threshold level.
Claim 18
Independent Claim
173 words
A system for providing an accurate binary representation of the frequency of an unknown signal comprising: (a) digital phase detector means for generating a digital error signal proportional to the difference in the frequency of said unknown signal and that of a reference signal, said digital error signal comprising a first pulse train with a pulse repetition rate proportional to the frequency difference between said unknown and reference signals and a second binary signal the state of which is indicative of whether the frequency of said reference signal is greater or less than that of said unknown signal, (b) digital closed loop means responsive to said digital error signal and operatively connected to equalize said reference signal with said unknown signal, said digital closed loop further providing a binary representation of the frequency of said reference signal, and (c) a carrier detector for monitoring the short term average power of said unknown signal and for inhibiting the generation of said first pulse train when said average power falls below a predetermined threshold level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-12 | 1982-09-11 | 1983-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-12 | 1986-09-11 | 1987-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-12 | 1990-09-11 | 1991-03-13 | $7700.00 | Window Closed / Lapsed |