Digital frequency multiplier

Claim 2

A digital frequency multiplier comprising: a first path and a second path, a first source of clock pulses and a second source of clock pulses for supplying said first and second paths respectively, divider means in said first path for dividing the first clock pulses relative to the incoming rate, first counter means in said first path, said first counter means having a first input for receiving an incoming frequency and for determining the number of pulses occuring from said first source during the period between sequential cycles of said incoming frequency, holding means for periodically holding the count determined by said first counter means updated at a rate dependant on the incoming frequency, second counter means in said second path for counting the number of clock pulses from said second source, comparator means connected to receive the outputs of the first and second paths respectively to produce an output signal having a repetition frequency which is a multiple of the incoming frequency, and inhibit means for momentarily inhibiting a change in the count provided by said second counter means whenever the holding means is being updated.

Claim 3

A multiplier according to claim 1, including second inhibit means for momentarily inhibiting updating of the count from said first counter means to said holding means whenever a change in the comparator output occurs.

Claim 4

A multiplier according to claim 2, wherein said holding means comprises a first latch for holding the first counter output and said second inhibit means comprises a second latch for inhibiting loading of said first latch when a change in output from said comparator means is detected.

Claim 5

A multiplier according to claim 1, including common clock generator means for providing said first and second sources of clock pulses.

Claim 6

A multiplier according to claim 1, wherein said divider means is adapted to provide a reduction in the rate of clock pulses from said first source prior to receipt by said first counter means.

Claim 7

A multiplier according to claim 1, wherein modifier means are provided in said second path to allow a multiplication rate selected to be other than an integer.

Claim 8

A multiplier according to claim 1, wherein said comparator means is adapted to provide a change in the output signal whenever coincidence between the counts from said first and second paths is detected.

Claim 9

A multiplier according to claim 1, wherein said comparator means is integral with said second counter means.

Claim 10

A multiplier according to claim 8, wherein the comparator means is adapted to detect the count made available from said holding means relative to the count made available to an input of said second counter means.

Claim 11

A multiplier according to claim 1, wherein said divider means includes a clock counter for receiving the pulses from said first source and ratio switches for selecting the desired clock rate reduction produced at the output of said clock counter.

Claim 12

A multiplier according to claim 1, wherein said first counter means includes a period counter for counting the number of clock pulses received at its input during a cycle of the incoming frequency and said holding means are provided for holding the counter output for use during a subsequent operation cycle.

Claim 13

A multiplier according to claim 1, wherein synchronising means are provided prior to the first counter means to synchronise the incoming frequency to the clocks from said first source.

Claim 14

A multiplier according to claim 12, wherein said synchronising means comprises a synchronising latch and includes a monostable circuit connected to said synchronising latch to provide a narrow width synchronising pulse for controlling the first counter means.

Claim 15

A multiplier according to claim 1, wherein said second counter means comprises a down counter adapted to count down from a number dependent on that counted by said first counter means and said comparator means is provided within said second counter means to produce an output pulse when a zero count is detected.

Claim 16

A multiplier according to claim 1, wherein said second counter means comprises an up counter adapted to count up from zero to a predetermined number dependent on that counted from said first counter means and said comparator means is provided within said second counter means to produce an output pulse when the predetermined number is reached.

Claim 17

A multiplier according to claim 1, wherein said divider means is adapted to provide a reduction in the output from said first counter means prior to receipt by said comparator means.

Claim 18

A multiplier according to claim 1, wherein the divider means comprises an arithmetic divider for reducing the arithmetic output provided by the holding means prior to receipt by the comparator means.

Claim 19

A multiplier according to claim 17, wherein a second arithmetic divider is provided in said second path for reducing the arithmetic output provided by said second counter means prior to receipt by said comparator means.

Claim 20

A digital frequency multiplier comprising: a first path and a second path, a first source of clock pulses and a second source of clock pulses for supplying said first and second paths respectively, first counter means in said first path, said first counter means having a first input for receiving an incoming frequency and for determining the number of pulses occuring from said first source during the period between sequential cycles of said incoming frequency, divider means in said first path for dividing the first clock pulses relative to the incoming rate, second counter means in said second path for counting the number of clock pulses from said second source, comparator means connected to receive the outputs of the first and second paths respectively to produce an output signal having a repetition frequency which is a multiple of the incoming frequency, and holding means comprising a first latch is provided for holding the first counter output and a second latch is provided for inhibiting the loading of said first latch when a change in output from said comparator means is detected.

Claim 21

A digital frequency multiplier comprising: a first path and a second path, a first source of clock pulses and a second source of clock pulses for supplying said first and second paths respectively, first counter means in said first path, said first counter means having a first input for receiving an incoming frequency and for determining the number of pulses occuring from said first source during the period between sequential cycles of said incoming frequency, divider means in said first path for dividing the first clock pulses relative to the incoming rate, second counter means in said second path for counting the number of clock pulses from said second source, comparator means connected to receive the outputs of the first and second paths respectively to produce an output signal having a repetition frequency which is a multiple of the incoming frequency, and holding means comprising a first latch is provided for holding the first counter output and a second latch is provided for inhibiting the loading of said first latch when a change in output from said comparator means is detected.

Claim 22

A digital frequency multiplier comprising: a first path and a second path, a first source of clock pulses and a second source of clock pulses for applying said first and second paths respectively, first counter means in said first path, said first counter means having a first input for receiving an incoming frequency and for determining the number of pulses occuring from said first source during the period between sequential cycles of said incoming frequency, divider means in said first path for dividing the first clock pulses relative to the incoming rate, second counter means in said second path for counting the number of clock pulses from said second source, comparator means connected to receive the outputs of the first and second paths respectively to produce an output signal having a repetition frequency which is a multiple of the incoming frequency, and synchronising means are provided prior to said first counter means to synchronise the incoming frequency to the first source clocks, said synchronising means comprising a synchronising latch and a monotable circuit connected thereto to provide a narrow width pulse for controlling the first counter means.

Claim 23

A digital frequency multiplier comprising: a first path and a second path, a first source of clock pulses and a second source of clock pulses for applying said first and second paths respectively, first counter means in said first path, said first counter means having a first input for receiving an incoming frequency and for determining the number of pulses occuring from said first source during the period between sequential cycles of said incoming frequency, divider means in said first path for dividing the first clock pulses relative to the incoming rate, second counter means in said second path for counting the number of clock pulses from said second source, comparator means connected to receive the outputs of the first and second paths respectively to produce an output signal having a repetition frequency which is a multiple of the incoming frequency, and synchronising means are provided prior to said first counter means to synchronise the incoming frequency to the first source clocks, said synchronising means comprising a synchronising latch and a monotable circuit connected thereto to provide a narrow width pulse for controlling the first counter means.

Claim 26

A method according to claim 21, including the step of inhibiting the held pulse count whenever a change in the comparison step occurs.