US3935538A
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US
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Digital frequency-control circuit
Assignee: Robert Bosch GmbH
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Filing: 1974-08-21
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Granted: 1976-01-27
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Expires: 1994-08-21
Abstract
Abstract Clock pulses are multiplied by a ratio less than 1 of which the numerator is controlled by a reversible counter. The multiplier output pulses initiate new countdown cycles of a second counter beginning with the clock pulse following the onset of an input frequency pulse and ending with the clock pulse following the onset of the next input frequency pulse. The state of the count at the end of the cycle determines whether the reversible counter will be left unchanged, advanced, or counted back and hence, whether the multiplier output frequency will be left unchanged, increased or reduced. The initial countdown value of the second counter is provided by a long term store which determines the frequency multiplication ratio. The circuit is usable to multiply a variable input frequency in a vehicle brake anti-lock system.
Inventors
- 👤 Harald Kizler
- 👤 Bernd Przybyla
- 👤 Peter-Jurgen Schmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:21
CPC Classifications
H; H03; H03L; H03L7/00; B; B60; B60N; B60N2/00; B60N2/24; B60N2/32; B60T; B60T8/00; B60T8/17; B60T8/172; B62; B62D; B62D33/00; B62D33/06; B62D33/0612
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
130 words
A digital frequency control circuit comprising: a reversible counter; a digital multiplying stage arranged for control of one of its factors by said reversible counter, said multiplying stage (17) serving as a controlled variable frequency generator of said frequency control circuit; a frequency divider stage comprising a second counter (16) and a storage circuit, the content of which determines its frequency division factor, said content being arranged to be counted out repeatedly at the output frequency of said multiplier stage (17); and means for determining the content of said second counter (16) at the beginning of a new input signal (f E ) and for correctively changing the stored content of said reversible counter (15) in response thereto, said last-mentioned means serving as comparison means for the frequency control circuit.
Claim 2
Dependent Claim
130 words
A digital frequency control circuit comprising: a reversible counter; a digital multiplying stage arranged for control of one of its factors by said reversible counter, said multiplying stage (17) serving as a controlled variable frequency generator of said frequency control circuit; a frequency divider stage comprising a second counter (16) and a storage circuit, the content of which determines its frequency division factor, said content being arranged to be counted out repeatedly at the output frequency of said multiplier stage (17); and means for determining the content of said second counter (16) at the beginning of a new input signal (f E ) and for correctively changing the stored content of said reversible counter (15) in response thereto, said last-mentioned means serving as comparison means for the frequency control circuit.
Claim 3
Dependent Claim
49 words
A digital frequency control circuit as defined in claim 1 which comprises also a source of clock pulses supplying pulses to said multiplying stage and synchronizing means (10) for synchronizing trigger pulses of said input frequency (f E ) with the pulses provided by said source of clock pulses.
Claim 4
Dependent Claim
56 words
A digital frequency control circuit as defined in claim 2 which comprises also storage means for storing a fixed digital number and means for transferring said digital number repeatedly from said storage means (19) to said second counter (16) in response to successive trigger pulses (U 10 ) derived from said input frequency (f E ).
Claim 5
Dependent Claim
30 words
A digital frequency control circuit as defined in claim 3 in which said trigger pulses (U 10 ) are derived from pulses of said input frequency by said synchronizing means.
Claim 6
Dependent Claim
122 words
A digital frequency control circuit as defined in claim 2 in which said means serving as comparison means for said control circuit comprises decoding means (20,100) and a gate circuit (14) responsive thereto, in which, further, the output of said gate circuit (14) is connected to an input of said reversible counter (15) and said gate circuit and decoder circuit are so constituted that at least one count signal (U 14 ) is produced for altering the content of said reversible counter (15) in the appropriate direction when at the beginning of a new signal of input frequency (f E ) the counting cycle of said second counter (16) is short of terminating and likewise when said counting cycle is past termination.
Claim 7
Dependent Claim
20 words
A digital frequency control circuit as defined in claim 5 in which said second counter (16) is a count-down counter.
Claim 8
Dependent Claim
29 words
A digital frequency control circuit as defined in claim 6 in which the output of said synchronizing means (10) is connected to an input of said gate circuit (14).
Claim 9
Dependent Claim
97 words
A digital frequency control circuit as defined in claim 7 in which the outputs of said second counter (16) are connected with logic gates (21 to 23) contained in said decoding means (20) in such a way that said gate circuit (14) is blocked in the presence of signals (U 10 ) produced by said synchronizing means (10), whenever at the beginning of a new signal of input frequency (f E ) the counting cycle of said second counter (16) is completed by the content of said second counter (16) being counted down to a predetermined number.
Claim 10
Dependent Claim
19 words
A digital frequency control circuit as defined in claim 8 in which said predetermined number has the value 1.
Claim 11
Dependent Claim
19 words
A digital frequency control circuit as defined in claim 8 in which said predetermined number has the value 0.
Claim 12
Dependent Claim
54 words
A digital frequency control circuit as defined in claim 6 in which said decoding means (100) comprises a third counter (101) and in which means are provided for transferring the content of said second counter (16) to said third counter (101) at the beginning of a new signal of input frequency (f E ).
Claim 13
Dependent Claim
20 words
A digital frequency control circuit as defined in claim 11 in which said third counter (101) is a countdown counter.
Claim 14
Dependent Claim
30 words
A digital frequency control circuit as defined in claim 11 in which the output of said multiplier stage (17) is supplied to the counting input of said third counter (101).
Claim 15
Dependent Claim
66 words
A digital frequency control circuit as defined in claim 13 in which said decoding means (100) is provided with logic gates (102 to 104) arranged to control said gate circuit (14) in such a manner that the latter passes counting signals whenever at the beginning of a new signal of input frequency (f E ), the content of said third counter (101) is a predetermined number.
Claim 16
Dependent Claim
25 words
A digital frequency control circuit as defined in claim 14 in which said predetermined number related to said third counter (101) is greater than 0.
Claim 17
Dependent Claim
25 words
A digital frequency control circuit as defined in claim 15 in which said predetermined number related to said third counter (101) is greater than 1.
Claim 18
Dependent Claim
36 words
A digital frequency control circuit as defined in claim 14 in which the period during which said gate circuit (14) passes counting signals is equal to the duration of the count of said third counter (101).
Claim 19
Dependent Claim
66 words
A digital frequency control circuit as defined in claim 12 in which said decoding means (100) is provided with logic gates (102 to 104) arranged to control said gate circuit (14) in such a manner that said gate circuit (14) passes counting signals whenever the counting cycle of said second counter (16) has been completed before a new signal of input frequency (f E ) arrives.
Claim 20
Dependent Claim
29 words
A digital frequency control circuit as defined in claim 12 in which the output of said multiplier stage (17) is connected to one input of said gate circuit (14).
Claim 21
Dependent Claim
65 words
A digital frequency control circuit as defined in claim 5 in which said decoding means (20,100) is provided with a logic gate (23,102), the output of which is connected to the direction determining input of said reversible counter (15), whereby the direction of counting for incoming counting signals of said reversible counter (15) is controllable in response to the content of said second counter (16).
Claim 22
Dependent Claim
70 words
A digital frequency control circuit as defined in claim 11 in which said decoding means (20,100) is provided with a logic gate (23, 102), the output of which is connected to the direction controlling input of said reversible counter (15) in such a way as to control the direction of response of said reversible counter (15) to incoming count signals in accordance with the content of said third counter (101).
References Cited (Backward Citations)
US3633105A
Cited
US3781695A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-01-26 | 1979-07-28 | 1980-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-01-26 | 1983-07-28 | 1984-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-01-26 | 1987-07-28 | 1988-01-27 | $7700.00 | Window Closed / Lapsed |