US4244027A
Expired / Lapsed
US
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Digital open loop programmable frequency multiplier
Assignee: RCA Corp
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Filing: 1979-03-19
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Granted: 1981-01-06
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Expires: 1999-03-19
Abstract
Abstract A circuit arrangement for multiplying the frequency f x of an input signal by digital techniques is disclosed. A digital counter driven by a reference oscillator establishes the ratio of the reference frequency to signal frequency. The binary representation of this ratio is applied to a binary divider circuit and divided by the frequency multiplying factor M. The quotient produced is applied to program a presettable binary down-counter operating on the reference frequency f o to produce an output frequency Mf x where the components of the reference frequency are caused to cancel out.
Inventors
- 👤 Sol Shai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:23
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
176 words
A frequency multiplier comprising: means for supplying an input signal having an input frequency; means for supplying a reference signal having a reference frequency; means for supplying a first group of binary signals representing a multiplication factor by which said input frequency is to be multiplied; means responsive to said input and reference signals for generating a second group of binary signals representing the number of cycles of said reference signal in a predetermined number cycles of said input signal; means responsive to said first and second groups of binary signals for dividing said number of cycles of said reference signal in said predetermined number of cycles of said input signal by a divisor proportional to said multiplication factor to produce a third group of binary signals representing the quotient of said division; and means responsive to said reference signal and said third group of binary signals for dividing said reference frequency of said quotient to produce an output signal having a frequency substantially equal to the product of said input frequency times said multiplication factor.
Claim 2
Dependent Claim
176 words
A frequency multiplier comprising: means for supplying an input signal having an input frequency; means for supplying a reference signal having a reference frequency; means for supplying a first group of binary signals representing a multiplication factor by which said input frequency is to be multiplied; means responsive to said input and reference signals for generating a second group of binary signals representing the number of cycles of said reference signal in a predetermined number cycles of said input signal; means responsive to said first and second groups of binary signals for dividing said number of cycles of said reference signal in said predetermined number of cycles of said input signal by a divisor proportional to said multiplication factor to produce a third group of binary signals representing the quotient of said division; and means responsive to said reference signal and said third group of binary signals for dividing said reference frequency of said quotient to produce an output signal having a frequency substantially equal to the product of said input frequency times said multiplication factor.
Claim 3
Dependent Claim
27 words
A frequency multiplier as set forth in claim 1 wherein said last means includes a divide-by-two means for causing said output signal to be a square-wave signal.
Claim 4
Dependent Claim
141 words
A frequency multiplier as set forth in claim 2 wherein said next to last means further includes a first digital binary divider responsive to said first and second groups of binary signals for dividing said number of cycles of said reference frequency signal in said predetermined number of cycles of said input signal by said multiplication factor to produce an intermediate quotient represented by a fourth group of binary signals; and a second binary divider responsive to said fourth group of binary signals and a fifth group of binary signals representing a constant times said predetermined number of cycles of said input signal for dividing said intermediate quotient represented by said fourth group of binary signals by said constant times said predetermined number of cycles of said input signal to produce said quotient represented by said third group of binary signals.
Claim 5
Dependent Claim
172 words
A digital, programmable frequency multiplier for multiplying the frequency of an input signal to produce an output signal having a multiplied frequency, comprising: means for supplying a reference signal having a reference frequency substantially higher than said multiplied frequency; means responsive to said input signal and to said reference signal for generating a first group of binary signals representing a number proportional to the ratio of said reference frequency to said input frequency; means responsive to said first group of binary signals for dividing said number represented thereby by a determinable factor to generate a second group of binary signals representing the quotient of the division; and a presettable frequency down-counter divider responsive to said second group of binary signals and said reference signal; said presettable frequency down-counter being preset to a preset number in response to said second group of binary signals; said presettable frequency down-counter generating said output signal by providing on output pulse for each successive number of cycles of said reference signal substantially equal to said preset number.
Claim 6
Dependent Claim
172 words
A digital, programmable frequency multiplier for multiplying the frequency of an input signal to produce an output signal having a multiplied frequency, comprising: means for supplying a reference signal having a reference frequency substantially higher than said multiplied frequency; means responsive to said input signal and to said reference signal for generating a first group of binary signals representing a number proportional to the ratio of said reference frequency to said input frequency; means responsive to said first group of binary signals for dividing said number represented thereby by a determinable factor to generate a second group of binary signals representing the quotient of the division; and a presettable frequency down-counter divider responsive to said second group of binary signals and said reference signal; said presettable frequency down-counter being preset to a preset number in response to said second group of binary signals; said presettable frequency down-counter generating said output signal by providing on output pulse for each successive number of cycles of said reference signal substantially equal to said preset number.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-06 | 1984-07-07 | 1985-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-06 | 1988-07-07 | 1989-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-06 | 1992-07-07 | 1993-01-06 | $7700.00 | Window Closed / Lapsed |