US4025866A
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Open loop digital frequency multiplier
Assignee: National Aeronautics and Space Administration
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Filing: 1975-11-10
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Granted: 1977-05-24
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Expires: 1995-11-10
Abstract
Abstract An open loop digital frequency multiplier with a multiplied output synchonized to low frequency clock pulses. The system includes a multi-stage digital counter which provides a pulse output as a function of an integer divisor. The integer divisor and the timing or counting cycle of the counter are interrelated to the frequency of a clock input. The counting cycle is controlled by a one-shot multivibrator which, in turn, is driven by a reference frequency input.
Inventors
- 👤 with respect to an invention of Fletcher James C. Administrator of the National Aeronautics and Space Administration
- 👤 Robert Clark Moore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:28
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; H; H03; H03K; H03K21/00; H03K21/38
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
192 words
An open-loop digital frequency multiplier for multiplying a low frequency of clock pulses by a desired multiple M to produce high frequency output pulses which are synchronized to low frequency reference pulses, said multiplier comprising: a source of clock pulses at a low reference frequency, a source of higher frequency clock input pulses, a multi-stage digital counter means which produces as its output said high frequency output pulses, reset means coupled to said source of reference frequency clock pulses and responsive thereto for providing to said digital counter means repetitive reset pulses having a pulse width of time duration T for repetitively resetting said counter means as periodic occurrences corresponding to said reference frequency pulse occurrences, means coupling said higher frequency clock input pulses to the digital counter means, said digital counter means including means for dividing said higher input frequency of clock input pulses by an integer value N whereby the output frequency of said output pulses produced by the digital counter means represents the product of said reference frequency and the multiplier function M and equals the ratio of said higher frequency of clock input pulses and the integer N.
Claim 2
Dependent Claim
192 words
An open-loop digital frequency multiplier for multiplying a low frequency of clock pulses by a desired multiple M to produce high frequency output pulses which are synchronized to low frequency reference pulses, said multiplier comprising: a source of clock pulses at a low reference frequency, a source of higher frequency clock input pulses, a multi-stage digital counter means which produces as its output said high frequency output pulses, reset means coupled to said source of reference frequency clock pulses and responsive thereto for providing to said digital counter means repetitive reset pulses having a pulse width of time duration T for repetitively resetting said counter means as periodic occurrences corresponding to said reference frequency pulse occurrences, means coupling said higher frequency clock input pulses to the digital counter means, said digital counter means including means for dividing said higher input frequency of clock input pulses by an integer value N whereby the output frequency of said output pulses produced by the digital counter means represents the product of said reference frequency and the multiplier function M and equals the ratio of said higher frequency of clock input pulses and the integer N.
Claim 3
Dependent Claim
63 words
The apparatus as defined in claim 1 wherein the frequency of said input frequency clock pulses is between the limits determined by the following equation: ##EQU3## where N= the integer value M= the frequency of said output pulses divided by the frequency of the reference input pulses F ref = the reference frequency F osc = the frequency of the input clock pulses
Claim 4
Dependent Claim
20 words
The apparatus as defined in claim 2 wherein the integer value is a power of the number two or ten.
Claim 5
Dependent Claim
19 words
The apparatus as defined in claim 3 wherein said timing period has a pulse width T equal to ##EQU4##
Claim 6
Dependent Claim
24 words
The apparatus as defined in claim 4 wherein said input pulses are at a frequency equal to MNF ref and equal to NF out.
Claim 7
Dependent Claim
46 words
The multiplier as defined in claim 1 wherein said reset means comprises a one-shot multivibrator means whereby the reset pulses are generated at instances corresponding to the falling edges of said reference frequency source pulses and said counter means is reset during said time duration T.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-23 | 1980-11-22 | 1981-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-23 | 1984-11-22 | 1985-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-23 | 1988-11-22 | 1989-05-24 | $7700.00 | Window Closed / Lapsed |