Digital frequency multiplying system

Claim 1

A digital frequency multiplier responsive to an input pulse train to produce an output pulse train at a higher frequency comprising: an oscillator, a first counter connected to said oscillator, a digital store, a comparator circuit connected to said first counter and said digital store to produce a signal indicative of coincidence between the number in said digital store and the count in said first counter, the succession of such signals being the output pulse train, a further connection between said comparator circuit and said first counter to reset the counter on occurrence of said signal, a second counter connected to receive said output pulse train, a sequence detector, connected to said input pulse train and to the output of said second counter, producing control signals indicative of coincidence or absence thereof between the input pulse train and the output of said second counter, means coupling said control signals to said digital store to increase the number stored therein if the output of the second counter occurs before the corresponding pulse of the input pulse train and to decrease the number stored therein if the output of the second counter occurs after the corresponding pulse of the input pulse train and means connecting said sequence detector and said second counter to reset the second counter on the occurrence of both inputs to said sequence detector.