Binary rate multiplier with means for spacing output signals

Claim 1

In a binary rate multiplier for producing N times f 0 output signals, of the type having first input means for receiving signals representing the value of N, second input means for receiving signals at a rate f 0 , programmable divide-by-N means preset to said value of N from said first input means by said second input signal means and responsive to said output signals for producing a carry signal after N output signals have been counted, clocking means for producing clocking signals at a rate f c not less than N MAX times f 0 , where N MAX is the maximum value of N, and gating means responsive to said carry signal for passing N clocking signals for each signal from said second input means, the improvement comprising: clock adjustment means responsive to the N value and to the rate f 0 for adjusting the clock signal rate to approximately (N+1) times f 0 .

Claim 6

A method for producing substantially evenly spaced output signals from a binary rate multiplier comprising the steps of: producing maximum desired rate clock pulses; storing a value N representing the frequency multiplier; adjusting the rate of said clock pulses to a value approximating (N+1) times f 0 , the rate of the signals to be multiplied; and controlling an output signal gating means with the adjusted clock pulses; enabling the output gating means for N output pulses for each signal to be multiplied.

Claim 7

A method for producing substantially evenly spaced output signals from a binary rate multiplier comprising the steps of: producing maximum desired rate clock pulses; storing a value N representing the frequency multiplier; adjusting the rate of said clock pulses to a value approximating (N+1) times f 0 , the rate of the signals to be multiplied; and controlling an output signal gating means with the adjusted clock pulses; enabling the output gating means for N output pulses for each signal to be multiplied.