← Back to Patent Explorer
US3753125A Expired / Lapsed US ⏱️ 0.0 years remaining

Frequency multiplier circuit

Assignee: NEC Corp
•
Filing: 1972-07-27
•
Granted: 1973-08-14
•
Expires: 1992-07-27
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Apparatus for multiplying an input frequency by a number A/B where A and B are integers and A > B. During one period of the input frequency, fin , pulses at a rate fo/A are accumulated and held. Pulses at a rate fo/B are continuously counted and for each P pulses of said latter pulses an output pulse is generated. Since P is the number of fo/A rate pulses occurring during one period of fin, the output pulse rate is fin X A/B. Additional means are provided for averaging the period of fin by counting the fo/A rate pulses for a multiple of periods of fin and obtaining the number P occurring during a single period by effectively dividing the accumulated pulses by said multiple.

Inventors

  • 👤 M Ishikawa
  • 👤 K Ota

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 23:21
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/62; G06F7/68

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 143 words
A frequency multiplier circuit for converting the frequency of an input signal to an output frequency equal to the input frequency multiplied by A/B (A and B are integers, A > B) comprising: means for producing a reference signal having a reference frequency fo; means for providing from said reference signal a first intermediate signal having frequency fo/A; means for providing from said reference signal a second intermediate signal having frequency fo/B; a first pulse counter for counting the pulses of said first intermediate signal for one period of said onput signAl to produce an output signal representative of the number of pulses counted; a second pulse counter for counting the pulses of said second intermediate signal; means for detecting the coincidence between the outputs of said first and second pulse counters, whereby the output of said detecting means has said output frequency.
Claim 2
Dependent Claim 143 words
A frequency multiplier circuit for converting the frequency of an input signal to an output frequency equal to the input frequency multiplied by A/B (A and B are integers, A > B) comprising: means for producing a reference signal having a reference frequency fo; means for providing from said reference signal a first intermediate signal having frequency fo/A; means for providing from said reference signal a second intermediate signal having frequency fo/B; a first pulse counter for counting the pulses of said first intermediate signal for one period of said onput signAl to produce an output signal representative of the number of pulses counted; a second pulse counter for counting the pulses of said second intermediate signal; means for detecting the coincidence between the outputs of said first and second pulse counters, whereby the output of said detecting means has said output frequency.
Claim 3
Dependent Claim 70 words
Apparatus for multiplying an input frequency fin by A/B where A > B, comprising, a. means for accumulating and holding a number, P, representing the number of pulses of frequency fo/A occurring during one period of fin, where fo/A > fin , and b. means responsive to pulses at a rate fo/B and to said number, P, for providing an output pulse for every P pulses at a rate fo/B.
Claim 4
Dependent Claim 70 words
Apparatus for multiplying an input frequency fin by A/B where A > B, comprising, a. means for accumulating and holding a number, P, representing the number of pulses of frequency fo/A occurring during one period of fin, where fo/A > fin , and b. means responsive to pulses at a rate fo/B and to said number, P, for providing an output pulse for every P pulses at a rate fo/B.
Claim 5
Dependent Claim 98 words
Apparatus as claimed in claim 2 wherein means for accumulating and holding comprises, a. means for generating a frequency fo, b. divider means for dividing fo by A resulting in a pulse train of frequency fo/A, c. a holding circuit for holding a number applied thereto, d. first means for counting said pulses at frequency fo/A during a period which is an integral multiple of the period of fin, where said integral multiple may be 1, 2, 3 . . . etc., and for transferring the number counted divided by said integral multiple to said holding circuit means.
Claim 6
Dependent Claim 28 words
Apparatus as claimed in claim 3 further comprising second divider means for dividing said frequency fo by B to obtain a pulse train at a frequency of fo/B.
Claim 7
Dependent Claim 70 words
Apparatus as claimed in claim 4 wherein said means for providing output pulses comprises, a. second counter means for counting said pulses occurring at the rate fo/B, b. comparator means responsive to the numbers in said holding circuit means and said second counter means, respectively, for providing an output pulse when said numbers are equal, and c. means responsive to each said output pulse for clearing said second counter means.
Claim 8
Dependent Claim 107 words
Apparatus as claimed in claim 5 wherein said first means comprises, a. third counter means responsive to input frequency fin for providing output pulses defining the beginning and end of said period which is an integral multiple of the period of fin, and b. first counter means responsive to the pulses from said third counter for counting said fo/A rate pulses starting with the beginning of each said period and for transferring a portion of the count accumulated therein at the end of said period, said portion corresponding to the total number accumulated divided by N where N is the integral multiple of said period of fin.

References Cited (Backward Citations)

US3581116A Cited
US3551826A Cited
US3605026A Cited
US3660842A Cited
US3673391A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-08-13 1977-02-12 1977-08-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-08-13 1981-02-12 1981-08-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-08-13 1985-02-12 1985-08-14 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag