Apparatus for digital frequency multiplication

Claim 2

Apparatus for digital frequency multiplication comprising: a. first AND logic gating means adapted to receive an input pulse train having a frequency fin, each pulse width defining one iteration; b. numerator shift register means having digital contents N, connected to the input of said first AND gating means, said first AND logic gating means when enabled by said signal fin having the output N, c. second AND logic gating means; d. denominator shift register means having digital contents D connected to the input of said second AND logic gating means; e. accumulator register means coupled to the outputs of said AND gates and having digital contents R; f. comparative means connected to said accumulator register means to compare said R with a datum level and for delivering an output signal f0 when R < datum level and for delivering an enabling signal to said second AND gating means which then has an output D, the contents of the accumulator register means becoming: Rn 1 Rn - N + D where Rn the contents of the accumulator register at the nth iteration where n 0, 1, 2, 3, . . . n; Rn 1 the contents of the accumulator register means at the (n + 1)th iteration; and f0 (N/D) fin

Claim 3

Apparatus for digital frequency multiplication comprising: a. first AND logic gating means adapted to receive an input pulse train having a frequency fin, each pulse width defining one iteration; b. numerator shift register means having digital contents N; c. first weighting means connected to the output of said numerator shift register means for delivering weighted numerator digital contents K1N where K1 may be any number rational or irrational; d. first means for switching connected to receive the digital contents N, K1N, and connected to the input of said first AND logic gating means for delivering N or K1N to said first AND logic gating means upon receipt of an enabling signal; e. second AND logic gating means; f. denominator shift register means having digital contents D; g. second weighting means connected to the output of said denominator shift register means for delivering weighted denominator digital contents K2D where K2 may be any number rational or irrational; h. second means for switching connected to receive the digital contents D, K2D, and connected to the input of said Second AND logic gating means for delivering D or K2D to said second AND logic gating means upon receipt of an enabling signal; i. accumulator register means coupled to the outputs of said AND logic gates, and having digital contents R; j. comparator means connected to said accumulator register means to compare said R with 0 and with K2D, and for delivering an output signal f0 when R < 0 or R < K2D, and for delivering an enabling signal to said second AND gating means, where R 0 the contents of the accumulator means becoming: Rn 1 R1 - N (or K1N) + D (or K2D) where Rn the contents of the accumulator register at the nth iteration, n 0, 1, 2, 3, . . . n; Rn 1 the contents of the remainder register at the (n + 1)th iteration and f0 (N (or K1N)/D (or K2D)) X fin

Claim 4

Apparatus for digital frequency multiplication comprising: a. first AND logic gating means adapted to receive an input pulse train having a frequency fin, each pulse width defining one iteration; b. numerator shift register means having digital contents N; c. first weighting means connected to the output of said numerator shift register means for delivering weighted numerator digital contents K1N where K1 may be any number rational or irrational; d. first means for switching connected to receive the digital contents N, K1N, and connected to the input of said first AND logic gating means for delivering N or K1N to said first AND logic gating means upon receipt of an enabling signal; e. second AND logic gating means; f. denominator shift register means having digital contents D; g. second weighting means connected to the output of said denominator shift register means for delivering weighted denominator digital contents K2D where K2 may be any number rational or irrational; h. second means for switching connected to receive the digital contents D, K2D, and connected to the input of said Second AND logic gating means for delivering D or K2D to said second AND logic gating means upon receipt of an enabling signal; i. accumulator register means coupled to the outputs of said AND logic gates, and having digital contents R; j. comparator means connected to said accumulator register means to compare said R with 0 and with K2D, and for delivering an output signal f0 when R < 0 or R < K2D, and for delivering an enabling signal to said second AND gating means, where R 0 the contents of the accumulator means becoming: Rn 1 R1 - N (or K1N) + D (or K2D) where Rn the contents of the accumulator register at the nth iteration, n 0, 1, 2, 3, . . . n; Rn 1 the contents of the remainder register at the (n + 1)th iteration and f0 (N (or K1N)/D (or K2D)) X fin

Claim 5

Apparatus for digital frequency multiplication according to claim 2 in which said first weighting means is an n bit shift register where n, may have 2, 3, 4 . . . n bits and said second weighting means is an n bit shift register where n may have 2, 3, 4 . . . bits.

Claim 6

Apparatus for digital frequency multiplication according to claim 1 in which said accumulator register means comprises an adder and a remainder shift register, the output of said remainder shift register being fed back as a first input to said adder, a second input to said adder being the algebraic summation of the output of said first and second AND logic gating means, the output of said adder being the digital contents R.

Claim 7

Apparatus for digital frequency multiplication according to claim 2 in which said accumulator register means comprises an adder and a remainder shift register, the output of said remainder shift register being fed back as a first input to said adder, a second input to said adder being the algebraic summation of the outputs of said first and second logic gating means, the output of said adder being the digital contents R.