Digital differential analyzer employing multiple overflow bits

Claim 2

In a digital differential integrator of the type wherein there is an adder, an integrand register and an accumulator register, and during each iteration said integrand register and accumulator register have their contents shifted from the least significant bit positions serially into said adder to be added, said shift occurring a number of times determined by the length of said registers, and the integrand register contents are circulated back through its most significant bit position while being shifted into said adder, and the adder sum is shifted into said accumulator register through its most significant bit position, the improvement comprising: means for deriving as carry overflow a multibit binary number comprising a predetermined plurality of the most significant bits of the adder sum being entered into said accumulator register for each completion of the shift of the integrand and accumulator register contents through said adder, and means for resetting the most significant bit positions of said accumulator register assigned for occupation by said predetermined plurality of significant bits.

Claim 3

In a digital differential integrator as recited in claim 1 wherein said means for deriving as carry overflow one or more of the most significant bits of the adder sum being entered into said accumulator register for each completion of the shifT of the integrand and accumulator register contents through said adder comprises: a buffer register having as many bit positions as are in said carry overflow, means for transferring to said buffer register the contents of the one or more most significant bit positions of said accumulator register holding said carry overflow bits at each completion of the shift of the contents of the integrand and accumulator registers to said adder.

Claim 4

In a digital differential integrator as recited in claim 1 wherein said means for deriving as carry overflow one or more of the most significant bits of the adder sum being entered into said accumulator register for each completion of the shift of the integrand and accumulator register contents through said adder comprises: a buffer register having as many bit positions as are in said carry overflow, gate means for directing during each iteration the one or more significant bits in the output of said adder into said buffer register and the remainder of the output of said adder into said accumulator register.

Claim 5

Apparatus as recited in claim 3 wherein said gate means includes a first and a second gate means, means coupling the output of said adder to one input of said first and second gate means, means coupling the output of said first gate means to the most significant bit stage of said accumulator register, means coupling the output of said second gate means to the most significant stage of said buffer register, and means for enabling said first gate means and disenabling said second gate means until the least significant bit of said one or more significant bits appears at the output of said adder when said first gate means is disenabled and said second gate means is enabled.

Claim 6

In a digital differential integrator of the type wherein there is an adder, an integrand register and an accumulator register, and during each iteration said integrand register and accumulator register have their contents shifted from the least significant bit positions serially into said adder, said shift occurring a number of times determined by the length of said registers, and the integrand register contents are circulated back through its most significant bit position while being shifted into said adder, and the adder sum is shifted into said accumulator register through its most significant bit position, the improvement comprising: means for deriving carry overflow in the form of a multibit binary number from a predetermined plurality of the most significant bit positions of said accumulator register upon each completion of the shift of the contents of the integrand and accumulator registers through said adder, and means for resetting said accumulator most significant bit positions from which said carry overflow has been derived prior to commencing the next shift of integrand and accumulator contents into said adder.

Claim 7

In a digital differential integrator of the type wherein there is an adder, an integrand register and an accumulator register, and during each iteration said integrand register and accumulator register have their contents shifted from the least significant bit positions serially into said adder, said shift occurring a number of times determined by the length of said registers, and the integrand register contents are circulated back through its most significant bit position while being shifted into said adder, and the adder sum is shifted into said accumulator register through its most significant bit position, the improvement comprising: means for deriving carry overflow in the form of a multibit binary number from a predetermined plurality of the most significant bit positions of said accumulator register upon each completion of the shift of the contents of the integrand and accumulator registers through said adder, and means for resetting said accumulator most significant bit positions from which said carry overflow has been derived prior to commencing the next shift of integrand and accumulator contents into said adder.

Claim 8

In a digital differential integrator as recited in claim 5 wherein said means for deriving carry overflow from one or more of the most significant bit positions of said accumulator register includes a buffer register, and means for transferring the contents of said one or more most significant bit positions of said accumulator register into said buffer register upon each completion of a shift of the contents of said accumulator and integrand register into said adder.

Claim 9

A digital differential integrator having an adder means, an integrand register, an accumulator register, means for shifting serially the contents of said integrand and accumulator registers from the least significant bit stages into said adder means to be added, means for circulating the contents of said integrand register which are being shifted from its least significant bit position to its most significant bit position, means for inserting the sum output of said adder means into said accumulator register through its most significant bit position, means for deriving A carry overflow output from one or more of the most significant bit stages of said accumulator register at the end of the addition by said adder means of the integrand and accumulator registers, and means for resetting the accumulator stages from which carry overflow has been derived.

Claim 10

A digital differential integrator having an adder means, an integrand register, an accumulator register, means for shifting serially the contents of said integrand and accumulator registers from the least significant bit stages into said adder means to be added, means for circulating the contents of said integrand register which are being shifted from its least significant bit position to its most significant bit position, means for inserting the sum output of said adder means into said accumulator register through its most significant bit position, means for deriving A carry overflow output from one or more of the most significant bit stages of said accumulator register at the end of the addition by said adder means of the integrand and accumulator registers, and means for resetting the accumulator stages from which carry overflow has been derived.

Claim 11

A digital differential integrator having an adder means, an integrand register, an accumulator register, means for shifting serially the contents of said integrand and accumulator registers from the least significant bit stages into said adder means to be added, means for circulating the contents of said integrand register which are being shifted from its least significant bit position to its most significant bit position, a buffer register, and gate means for inserting all of the sum output of said adder means into said accumulator register through its most significant bit position except for a predetermined number of the most significant bits in said sum which are inserted by said gate means into said buffer register.

Claim 12

A digital differential integrator having an adder means, an integrand register, an accumulator register, means for shifting serially the contents of said integrand and accumulator registers from the least significant bit stages into said adder means to be added, means for circulating the contents of said integrand register which are being shifted from its least significant bit position to its most significant bit position, a buffer register, and gate means for inserting all of the sum output of said adder means into said accumulator register through its most significant bit position except for a predetermined number of the most significant bits in said sum which are inserted by said gate means into said buffer register.

Claim 13

Apparatus as recited in claim 8 wherein said gate means includes a first and second gate means, means coupling the output of said adder to one input of said first and second gate means, means coupling the output of said first gate means to the most significant digit stage of said accumulator register, means coupling the output of said second gate means to the most significant stage of said buffer register, and means for enabling said first gate means and disenabling said second gate means until the least significant bit of said one or more significant bits appears at the output of said adder when said first gate means is disenabled and said second gate means is enabled.

Claim 14

In a numerical control machine tool system of the type wherein the distance a machine tool table is to move along an axis is established by a motion command number which is converted into a motion command pulse train by a digital differential integrator circuit, said motion command pulse train being applied to a following error register, the output of which is used to drive a motor which moves the machine tool table, a feedback transducer converts the machine tool table motion into pulses which are then applied to the error register to reduce the contents established therein by said motion command pulse train, the improvement comprising, means for periodically deriving from said digital differential integrator circuit a carry overflow in the form of a several bit long binary number, means for accumulating the output of said feedback transducer over the interval between derivations of said carry overflow from said digital differential integrator, means for algebraically adding said binary number to the contents of said following error register to produce a first sum, means for algebraically adding said first sum with the accumulated output of said feedback transducer to produce a second sum, means for entering said second sum into said following error register, digital to analog converter means to which said following error register contents are applied for converting them to an analog signal, and motor means responsive to said analog signal to drive said machine tool table along an axis of motion.

Claim 15

In a numerical control machine tool system of the type wherein the distance a machine tool table is to move along an axis is established by a motion command number which is converted into a motion command pulse train by a digital differential integrator circuit, said motion command pulse train being applied to a following error register, the output of which is used to drive a motor which moves the machine tool table, a feedback transducer converts the machine tool table motion into pulses which are then applied to the error register to reduce the contents established therein by said motion command pulse train, the improvement comprising, means for periodically deriving from said digital differential integrator circuit a carry overflow in the form of a several bit long binary number, means for accumulating the output of said feedback transducer over the interval between derivations of said carry overflow from said digital differential integrator, means for algebraically adding said binary number to the contents of said following error register to produce a first sum, means for algebraically adding said first sum with the accumulated output of said feedback transducer to produce a second sum, means for entering said second sum into said following error register, digital to analog converter means to which said following error register contents are applied for converting them to an analog signal, and motor means responsive to said analog signal to drive said machine tool table along an axis of motion.

Claim 16

An automated method using a computer having a memory and a temporary store, said computer operating as a digital differential integrator with an n bit overflow, wherein the computer performs the following steps: deriving an X integrand number from memory, deriving an X accumulator number from memory, adding said X integrand and X accumulator numbers to provide a sum, storing in memory said sum numbers, reading said sum from memory into temporary storage, transferring out from temporary storage the n most significant bits of said sum as carry overflow bits, transferring out from temporary storage all but the n most significant bits of said sum to provide an updated X accumulator number, and storing said updated X accumulator number in memory in place of said X accumulator number.

Claim 17

An automated method using a computer having a memory and a temporary store, said computer operating as a digital differential integrator with an n bit overflow, wherein the computer performs the following steps: deriving an X integrand number from memory, deriving an X accumulator number from memory, adding said X integrand and X accumulator numbers to provide a sum, storing in memory said sum numbers, reading said sum from memory into temporary storage, transferring out from temporary storage the n most significant bits of said sum as carry overflow bits, transferring out from temporary storage all but the n most significant bits of said sum to provide an updated X accumulator number, and storing said updated X accumulator number in memory in place of said X accumulator number.

Claim 18

The automated method recited in claim 11 wherein the step of transferring out from temporary store the n most significant bits of the sum stored in said temporary store as carry overflow bits includes generating an ''''AND'''' function of ''''1'''' bits together with each of said n most significant bits to produce carry overflow bits which are duplicates, and wherein the step of transferring out from said temporary store said updated X accumulator number includes generating an ''''AND'''' function of ''''1'''' bits with each of the bits of the number in said temporary store except said n most significant bits to transfer out said updated X accumulator number.