Digital frequency-lock circuit

Claim 1

A digital frequency-lock circuit comprising a fixed frequency source, a rate multiplier means having a signal output, a multiplier control input and a signal input connected to an output of said frequency source, an up/down counter means having an enable input, a clock input, an up/down control input and a signal output for providing an output signal representing a digital word stored in said counter means, first circuit means connecting said signal output of said counter means to said multiplier control input of said rate multiplier means, input terminal means arranged to be connected to a source of an input signal having a frequency to be monitored, differentiator means for converting a cycle of said input signal to output signals defining a corresponding time period, second counter means having a clock input, a clear input and a carry output for providing an output signal representative of a predetermined count in said counter means, flip-flop means having a set input, a clock input and a clear input and a first output corresponding to said set input, second circuit means for applying said output signals from said differentiator means to said clear inputs of said flip-flop means and said second counter means, third circuit means connecting said first output of said flip-flop means to said up/down control input of said up/down counter means, signal gating means having an input means connected to receive said output signals from said differentiator means, an output connected to said enable input of said up/down counter means, and a gate control input connected to receive said carry output of said counter means, and fourth circuit means connecting said signal output to said clock inputs of said up/down counter means, said flip-flop means and said second counter means.