CCD clock driver circuit

Claim 2

A clock drive circuit for a CCD capacitive load which in response to an input clock signal provides driving current into such load, comprising: (a) a plurality of driver circuits connected in parallel, each having an input and output and two switching transistors connected in series which alternately change state in response to the level of said clock signal; (b) a resistor and a diode connected in parallel between the series connection of the two switching transistors and the output of the driver circuit; and (c) the input of each driver circuit being commonly connected to receive said input clock signal, and the output of each driver circuit being commonly connected to provide charging current to said capacitive load.

Claim 3

The invention as set forth in claim 1 wherein each said driver circuit is a CMOS circuit having two switching FETs.

Claim 4

A clock driver circuit for a CCD capacitive load which in response to an input clock signal provides driving current into such load, comprising: (a) a plurality of first driver circuits connected in parallel each having a common input and a common output and two switching transistors connected in series which alternately change state in response to the level of said clock signal, the inputs of said first driver circuits being connected to receive said clock signal; (b) a parallel combination of a resistor and a diode connected between the series connection of the two switching transistors and the output of each of said first driver circuits to provide short circuit protection for at least one of such first driver circuits switching transistors; and (c) the outputs of each of said first driver circuits being connected to provide charging current to said capacitive load.

Claim 5

A clock driver circuit for a CCD capacitive load which in response to an input clock signal provides driving current into such load, comprising: (a) a plurality of first driver circuits connected in parallel each having a common input and a common output and two switching transistors connected in series which alternately change state in response to the level of said clock signal, the inputs of said first driver circuits being connected to receive said clock signal; (b) a parallel combination of a resistor and a diode connected between the series connection of the two switching transistors and the output of each of said first driver circuits to provide short circuit protection for at least one of such first driver circuits switching transistors; and (c) the outputs of each of said first driver circuits being connected to provide charging current to said capacitive load.

Claim 6

The invention as set forth in claim 3 including a plurality of second driver circuits responsive to said clock signal and having outputs commonly connected to provide an input signal to each of said plurality of first driver circuits.