US4419593A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ultra fast driver circuit
Assignee: Honeywell Inc
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Filing: 1981-06-29
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Granted: 1983-12-06
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Expires: 2001-06-29
Abstract
Abstract A driver circuit in which a signal received at an input gate provides, at the output of the circuit, a signal having fast rise and fall times and high voltage swings. The input stage of the circuit includes two transistors coupled in a complementary emitter follower arrangement and the output stage of the circuit includes two transistors in a complementary common emitter amplifier arrangement. The circuit includes separate high speed and low speed signal paths.
Inventors
- 👤 Neal R. Butler
- 👤 Alan R. Carson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:24
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/12
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
212 words
A circuit comprising: A. input logic for receiving an input signal; B. output logic for providing an output signal in response to a drive current; C. logic means coupled to said input logic for providing said drive current in response to said input signal; D. means for coupling said drive current for receipt by said output logic; E. means for providing a high speed signal path and a low speed signal path, said high speed signal path including said means for coupling and said high speed signal path coupled between said logic means and said output logic, and said low speed signal path coupled between said input logic and said output logic, wherein said high and low speed signal paths are operative substantially independent of each other; F. wherein said logic means includes two transistors having their respective emitters coupled together and to said output logic; and G. wherein said output logic includes two transistors having their respective collectors coupled together and also includes two capacitive elements, one end of each of said elements coupled together and to the junction of the emitters of said transistor included in said logic means, and the other end of said elements coupled to the bases respectively of the two transistors included in said output logic.
Claim 2
Dependent Claim
212 words
A circuit comprising: A. input logic for receiving an input signal; B. output logic for providing an output signal in response to a drive current; C. logic means coupled to said input logic for providing said drive current in response to said input signal; D. means for coupling said drive current for receipt by said output logic; E. means for providing a high speed signal path and a low speed signal path, said high speed signal path including said means for coupling and said high speed signal path coupled between said logic means and said output logic, and said low speed signal path coupled between said input logic and said output logic, wherein said high and low speed signal paths are operative substantially independent of each other; F. wherein said logic means includes two transistors having their respective emitters coupled together and to said output logic; and G. wherein said output logic includes two transistors having their respective collectors coupled together and also includes two capacitive elements, one end of each of said elements coupled together and to the junction of the emitters of said transistor included in said logic means, and the other end of said elements coupled to the bases respectively of the two transistors included in said output logic.
Claim 3
Dependent Claim
41 words
A circuit as in claim 1 further comprising a termination network coupled to the junction of the collectors of said transistors included in said output logic and selected so as to be compatible with the electrical characteristics of a receiving device.
Claim 4
Dependent Claim
58 words
A circuit as in claim 1 wherein said input logic includes a gate having two inputs, one for receiving said input signal and the other for receiving a polarity signal, whereby the presence of a first state of said polarity signal makes said circuit inverting and wherein a second state of said polarity signal makes said circuit noninverting.
Claim 5
Dependent Claim
61 words
A circuit as in claim 1 wherein said input logic includes an input for receiving said input signal and also includes an output, and wherein said circuit further comprises means for coupling said output of said input logic to the base of one of said transistors included in said output logic, said means for coupling comprising said low speed signal path.
Claim 6
Dependent Claim
29 words
A circuit as in claim 1 wherein said logic means includes a voltage level shifting network coupled so that the voltage swing associated with said drive current is increased.
Claim 7
Dependent Claim
44 words
A circuit as in claim 5 wherein said network includes at least one diode means which has a relatively high power handling capability and which has a relatively long reverse recovery time when compared to high speed diodes normally used in high speed circuits.
Claim 8
Dependent Claim
130 words
A high speed circuit comprising: A. input logic for receiving an input signal; B. first and second transistors coupled in a complementary emitter follower arrangement, wherein the emitters of said transistors are coupled together and wherein the base of at least one of said transistors is coupled to said input logic; C. first and second capacitive elements each having one end coupled to the emitters of said first and second transistors; and D. third and fourth transistors each having collectors coupled together to provide an output of said circuit, wherein the base of said third transistor is coupled to the other end of one of said capacitive elements, and wherein the base of said fourth transistor is coupled to the other end of the other one of said capacitive elements.
Claim 9
Dependent Claim
130 words
A high speed circuit comprising: A. input logic for receiving an input signal; B. first and second transistors coupled in a complementary emitter follower arrangement, wherein the emitters of said transistors are coupled together and wherein the base of at least one of said transistors is coupled to said input logic; C. first and second capacitive elements each having one end coupled to the emitters of said first and second transistors; and D. third and fourth transistors each having collectors coupled together to provide an output of said circuit, wherein the base of said third transistor is coupled to the other end of one of said capacitive elements, and wherein the base of said fourth transistor is coupled to the other end of the other one of said capacitive elements.
Claim 10
Dependent Claim
24 words
A circuit as in claim 7 further comprising a low speed circuit path between said input logic and the base of said fourth transistor.
Claim 11
Dependent Claim
61 words
A circuit as in claim 7 further comprising first and second diode elements coupled between the junction of said input logic and the base of said second transistor and the base of said first transistor so as to provide a higher voltage swing in respone to said input signal, at the junction of the emitters of said first and second transistors.
Claim 12
Dependent Claim
40 words
A circuit as in claim 9 wherein said first and second diode elements have a relatively high power handling capability and a relatively long reverse recovery time when compared to high speed diode elements normally used in high speed circuits.
Claim 13
Dependent Claim
151 words
A circuit comprising: A. input logic for receiving an input signal; B. output logic for providing an output signal in response to a drive current, wherein said logic means includes a voltage level shifting network coupled so that the voltage swing associated with said drive current is increased; C. logic means coupled to said input logic for providing said drive current in response to said input signal; D. means for coupling said drive current for receipt by said output logic; and E. means for providing a high speed signal path and a low speed signal path, said high speed signal path including said means for coupling and said high speed signal path coupled between said logic means and said output logic, and said low speed signal path coupled between said input logic and said output logic, wherein said high and low speed signal paths are operative substantially independent of each other.
Claim 14
Dependent Claim
151 words
A circuit comprising: A. input logic for receiving an input signal; B. output logic for providing an output signal in response to a drive current, wherein said logic means includes a voltage level shifting network coupled so that the voltage swing associated with said drive current is increased; C. logic means coupled to said input logic for providing said drive current in response to said input signal; D. means for coupling said drive current for receipt by said output logic; and E. means for providing a high speed signal path and a low speed signal path, said high speed signal path including said means for coupling and said high speed signal path coupled between said logic means and said output logic, and said low speed signal path coupled between said input logic and said output logic, wherein said high and low speed signal paths are operative substantially independent of each other.
Claim 15
Dependent Claim
44 words
A circuit as in claim 11 wherein said network includes at least one diode means which has a relatively high power handling capability and which has a relatively long reverse recovery time when compared to high speed diodes normally used in high speed circuits.
Claim 16
Dependent Claim
155 words
A circuit comprising: A. input logic for receiving an input signal: B. output logic, having an input connection, for providing an output signal in response to a drive current; C. logic means coupled to said input logic for providing said drive circuit in response to said input signal; D. means for coupling said drive current for receipt by said output logic; E. means for providing a high speed signal path and a low speed signal path, said high speed signal path including said means for coupling and said high speed signal path coupled between said logic means and said output logic, and said low speed signal path coupled between said input logic and said output logic, wherein said high and low speed signal paths are operative substantially independent of each other; and F. wherein said logic means includes two transistors having their respective emitters coupled together and to said input connection of said output logic.
Claim 17
Dependent Claim
155 words
A circuit comprising: A. input logic for receiving an input signal: B. output logic, having an input connection, for providing an output signal in response to a drive current; C. logic means coupled to said input logic for providing said drive circuit in response to said input signal; D. means for coupling said drive current for receipt by said output logic; E. means for providing a high speed signal path and a low speed signal path, said high speed signal path including said means for coupling and said high speed signal path coupled between said logic means and said output logic, and said low speed signal path coupled between said input logic and said output logic, wherein said high and low speed signal paths are operative substantially independent of each other; and F. wherein said logic means includes two transistors having their respective emitters coupled together and to said input connection of said output logic.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-05 | 1987-06-06 | 1987-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-05 | 1991-06-06 | 1991-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-05 | 1995-06-06 | 1995-12-06 | $7700.00 | Window Closed / Lapsed |