High density memory with field shield

Claim 2

A dynamic random access memory comprising a semiconductor substrate having a given surface and a trench formed therein, said trench having a sidewall, a storage capacitor having a plate disposed within said trench, a bit/sense line disposed at said given surface, a transfer device having a control electrode disposed within said trench between the plate of said storage capacitor and said bit/sense line, and means including a field shield for electrically isolating said storage capacitor, said means including a field shield being located within said trench and disposed on the sidewall thereof.

Claim 3

A dynamic random access memory as set forth in claim 1 wherein said storage capacitor and said means including a field shield include a first conductive layer having an opening therein and insulated from said substrate along the sidewalls and bottom of said trench and said transfer device includes a second conductive layer having a first portion overlapping and insulated from said first conductive layer and a second portion disposed within the opening in said first conductive layer and insulated from said sidewall between said storage capacitor and said bit/sense line.

Claim 4

A dynamic random access memory as set forth in claim 1 wherein said trench includes a bottom surface and said sidewall has a lower portion and said storage capacitor is disposed along the bottom surface of said trench and along the lower portion of the sidewalls of said trench.

Claim 5

A dynamic random access memory as set forth in claim 1 wherein said trench includes an inner surface and said storage capacitor includes a first diffusion region in said semiconductor substrate along the inner surface of said trench.

Claim 6

A dynamic random access memory as set forth in claim 4 wherein said trench further includes a bottom and said sidewall has a lower portion and said diffusion region is disposed along the bottom and the lower portion of the sidewalls of said trench.

Claim 7

A dynamic random access memory as set forth in claim 5 wherein said means including a field shield is disposed between said diffusion region and the given surface of said semiconductor substrate.

Claim 8

A dynamic random access memory as set forth in claim 6 wherein said storage capacitor and said means including a field shield include a first conductive layer insulated from said semiconductor substrate.

Claim 9

A dynamic random access memory as set forth in claim 7 wherein said bit/sense line includes a second diffusion region and said transfer device is disposed between said first and second diffusion regions.

Claim 10

A dynamic random access memory as set forth in claim 8 wherein said first conductive layer has an opening therein between said first and second diffusion regions and said transfer device includes a second conductive layer disposed within said opening and insulated from said first conductive layer and from said semiconductor substrate.

Claim 11

A dynamic random access memory as set forth in claim 9 wherein said semiconductor substrate is of a P type conductivity, said first and second diffusion regions are of N type conductivity and said first and second conductive layers are doped polysilicon and further including an insulating material disposed within said trench extending to the given surface of said substrate and a metallic line disposed on said insulating material and connected to said second conductive layer.

Claim 12

A dynamic random access memory as set forth in claim 10 wherein said insulating material is polyimide and said metallic line is copper doped aluminum.

Claim 13

A memory comprising a semiconductor substrate having a major surface and a trench formed therein, said trench including a bottom and sidewalls having lower portions, a first diffusion region disposed within said substrate at the bottom and lower portions of the sidewalls of said trench, a second diffusion region disposed at the major surface of said substrate near said trench, a first insulating layer disposed along the bottom and sidewalls of said trench and the major surface of said substrate, a first conductive layer disposed on said first insulating layer and having an opening therein located between said first and second diffusion regions, a second insulating layer disposed on said first conductive layer, and a second conductive layer disposed on said second insulating layer and on said first insulating layer within the opening in said first conductive layer.

Claim 14

A memory comprising a semiconductor substrate having a major surface and a trench formed therein, said trench including a bottom and sidewalls having lower portions, a first diffusion region disposed within said substrate at the bottom and lower portions of the sidewalls of said trench, a second diffusion region disposed at the major surface of said substrate near said trench, a first insulating layer disposed along the bottom and sidewalls of said trench and the major surface of said substrate, a first conductive layer disposed on said first insulating layer and having an opening therein located between said first and second diffusion regions, a second insulating layer disposed on said first conductive layer, and a second conductive layer disposed on said second insulating layer and on said first insulating layer within the opening in said first conductive layer.

Claim 15

A memory as set forth in claim 12 further including insulating material disposed within said trench on said second conductive layer and extending to the major surface of said substrate and a metallic line disposed on said material and connected to said second conductive layer.

Claim 16

A memory as set forth in claim 13 wherein said substrate is silicon having P type conductivity, said first and second regions are of N type conductivity, said first and second insulating layers include silicon dioxide, said first and second conductive layers include polysilicon, said material is polyimide and said metallic line is copper doped aluminum.

Claim 17

A memory array comprising a semiconductor substrate having a major surface and first, second, third and fourth trenches formed therein, first and second bit/sense lines arranged parallel to each other, said first bit/sense line extending between said first and third trenches and said second bit/sense line extending between second and fourth trenches, first and second word lines arranged parallel to each other and orthogonal to said first and second bit/sense lines, said first word line extending between said first and second trenches and said second word line extending between said third and fourth trenches, first, second, third and fourth storage capacitors disposed within said first, second, third and fourth trenches, respectively, first and second transfer devices disposed within said first and second trenches, respectively, said first device being coupled to said first bit/sense line and said first word line and said second transfer device being coupled to said second bit/sense line and said first word line, third and fourth transfer devices disposed within said third and fourth trenches, respectively, said third device being coupled to said first bit/sense line and said second word line and said fourth device being coupled to said second bit/sense line and said second word line, said first, second, third and fourth transfer devices also being coupled to said first, second, third and fourth storage capacitors, respectively, and first, second, third and fourth field shields disposed between said first, second, third and fourth storage capacitors and the major surface of said substrate.

Claim 18

A memory array comprising a semiconductor substrate having a major surface and first, second, third and fourth trenches formed therein, first and second bit/sense lines arranged parallel to each other, said first bit/sense line extending between said first and third trenches and said second bit/sense line extending between second and fourth trenches, first and second word lines arranged parallel to each other and orthogonal to said first and second bit/sense lines, said first word line extending between said first and second trenches and said second word line extending between said third and fourth trenches, first, second, third and fourth storage capacitors disposed within said first, second, third and fourth trenches, respectively, first and second transfer devices disposed within said first and second trenches, respectively, said first device being coupled to said first bit/sense line and said first word line and said second transfer device being coupled to said second bit/sense line and said first word line, third and fourth transfer devices disposed within said third and fourth trenches, respectively, said third device being coupled to said first bit/sense line and said second word line and said fourth device being coupled to said second bit/sense line and said second word line, said first, second, third and fourth transfer devices also being coupled to said first, second, third and fourth storage capacitors, respectively, and first, second, third and fourth field shields disposed between said first, second, third and fourth storage capacitors and the major surface of said substrate.

Claim 19

A memory array as set forth in claim 15 wherein each of said storage capacitors includes a diffusion region disposed below the major surface of said semiconductor substrate, each of said first and second bit/sense lines includes a diffusion region disposed at the major surface of said semiconductor substrate and each of said word lines includes a metallic line.

Claim 20

A memory array as set forth in claim 16 wherein each of said storage capacitors is disposed at the bottom and along the lower portion of the sidewall of its respective trench.