EP0159824A2
Expired / Lapsed
EP
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Semiconductor device with recessed capacitor
Assignee: Toshiba Corp
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Filing: 1985-03-26
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Granted: —
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Expires: 2005-03-26
Abstract
Abstract A semiconductor dynamic random access memory or dRAM is disclosed, in which each memory cell (10) has a memory cell transistor (Qm) and a memory cell capacitor (Cm) which is charged to reflect the logic state of its memory cell, while each dummy cell (12) has a dummy cell transistor (Qd) and a dummy cell capacitor (Cd) which is adopted to be precharged to a voltage level. To set the capacitance ratio of the memory to the dummy cell capacitor, the memory cell capacitor (Cm) has two recesses (16a, 16b) while the dummy cell capacitor (Cd) has a single recess (18). A high impurity concentration region (20) is provided for suppressing the spread of depletion layers fromed around the recesses (16a, 16b) of the memory cell capacitor (Cm) when charge is stored therein, thereby preventing the depletion layers formed around the recesses (16a, 16b) from becoming contiguous to one another.
Inventors
- 👤 Yukihito C/O Patent Division Oowaki
- 👤 Fumio C/O Patent Division Horiguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 23:22
CPC Classifications
H; H10; H10B; H10B12/00; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; H10B12/30; H10B12/37
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
77 words
A semiconductor device including a capacitor (Cm) formed on a semiconductive substrate, said capacitor having a plurality of recesses (16a, 16b) formed on said substrate (14), characterized in that depletion layer spread suppressing means (20) is provided for suppressing the spread of depletion layers formed around said recesses (16a, 16b) of said capacitor when charge is stored therein, thereby preventing said depletion layers formed around said plurality of recesses (16a, 16b) from becoming contiguous to one another.
Claim 2
Dependent Claim
77 words
A semiconductor device including a capacitor (Cm) formed on a semiconductive substrate, said capacitor having a plurality of recesses (16a, 16b) formed on said substrate (14), characterized in that depletion layer spread suppressing means (20) is provided for suppressing the spread of depletion layers formed around said recesses (16a, 16b) of said capacitor when charge is stored therein, thereby preventing said depletion layers formed around said plurality of recesses (16a, 16b) from becoming contiguous to one another.
Claim 3
Dependent Claim
59 words
The device according to claim 1, characterized in that said depletion layer spread suppressing means comprises a semiconductive layer (20) surrounding said plurality of recesses of said capacitor and having the same conductivity type as the conductivity type of said substrate (4), said semiconductive region (20) having a higher impurity concentration than the impurity concentration of said substrate (14).
Claim 4
Dependent Claim
39 words
The device according to claim 2, characterized in that said semiconductive region comprises a well region (20) formed in said substrate (14) such that said plurality of recesses of said memory cell capacitor are located in said well region.
Claim 5
Dependent Claim
154 words
A semiconductor memory device comprising a plurality of memory cells (10) each having a memory cell transistor (Qm) and a memory cell capacitor (Cm) which is charged so as to reflect the logic state of its memory cell (10) and a plurality of dummy cells (12) each having a dummy cell transistor (Qd) and a dummy cell capacitor (Cd) which is adopted to be precharged to a selected voltage level, characterized in that each memory cell capacitor (Cm) is formed on said substrate and has two first recesses (16a, 16b) while each dummy cell capacitor (Cd) is formed on said substrate and has one second recess (18), and that depletion layer spread suppressing means (20) is provided for suppressing the spread of depletion layers formed around said first recesses (16a, 16b) of each said memory cell capacitor when charge is stored therein, thereby improving the charge storage efficiency of each said memory cell capacitor.
Claim 6
Dependent Claim
154 words
A semiconductor memory device comprising a plurality of memory cells (10) each having a memory cell transistor (Qm) and a memory cell capacitor (Cm) which is charged so as to reflect the logic state of its memory cell (10) and a plurality of dummy cells (12) each having a dummy cell transistor (Qd) and a dummy cell capacitor (Cd) which is adopted to be precharged to a selected voltage level, characterized in that each memory cell capacitor (Cm) is formed on said substrate and has two first recesses (16a, 16b) while each dummy cell capacitor (Cd) is formed on said substrate and has one second recess (18), and that depletion layer spread suppressing means (20) is provided for suppressing the spread of depletion layers formed around said first recesses (16a, 16b) of each said memory cell capacitor when charge is stored therein, thereby improving the charge storage efficiency of each said memory cell capacitor.
Claim 7
Dependent Claim
64 words
The device according to claim 4, characterized in that said depletion layer spread suppressing means comprises a semiconductive region (20) surrounding said two first recesses of said memory cell capacitor, excluding said memory cell transistor and having the same conductivity type as the conductivity type of said substrate, said semiconductive region (20) having a higher impurity concentration than the impurity concentration of said substrate'(14).
Claim 8
Dependent Claim
40 words
The device according to claim 5, characterized in that said semiconductive region comprises a well region (20) formed in said substrate (14) such that said two first recesses of said memory cell capacitor are located in said well region (20).
Claim 9
Dependent Claim
129 words
The device according to claim 6, characterized in that the sum of the lengths of the peripheries of said two recesses (16a, 16b) of each said memory cell capacitor is double the length of the periphery of said recess (18) of each said dummy cell capacitor, whereby, in an etching process for forming said first recesses (16a, 16b) and said second recess (18) which respectively determine the memory cell capacitance and the dummy cell capacitance, even if the planar shapes are changed due to an etching fabrication error, the peripheral length ratio of the first recesses (16a, 16b) to the second recess (18) after the processing is constant so that the capacitance ratio of said first recesses (16a, 16b) to said second recess (18) coincides with a predetermined value.
Claim 10
Dependent Claim
36 words
The device according to claim 7, characterized in that said first recesses (16a, 16b) and second recess (18) are formed simultaneously on said substrate by the same etching process such that they have an equal depth.
Claim 11
Dependent Claim
30 words
The device according to claim 8, characterized in that each of said first recess (16a, 16b) has the same planar shape as the planar shape of said second recess (18).
Claim 12
Dependent Claim
23 words
The device according to claim 9, characterized in that said first recesses (16a, 16b) and second recess (18) have a rectangular planar shape.
References Cited (Backward Citations)
No citation records indexed.
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