US4271418A
Expired / Lapsed
US
⏱️ 0.0 years remaining
VMOS Memory cell and method for making same
Assignee: American Microsystems Holding Corp
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Filing: 1979-10-29
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Granted: 1981-06-02
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Expires: 1999-10-29
Abstract
Abstract A semiconductor memory device is provided comprised of an integrated array of cells formed on a substrate in conjunction with parallel spaced-apart bit lines and conductive word lines that are perpendicular to the bit lines. A plurality of V-shaped recesses are located between and extend perpendicular to adjacent parallel bit lines. Two cells share each recess and each cell includes a VMOS transistor formed by one end portion of the recess and an isolated buried source region located under the adjacent bit line. A channel stop region is located between and isolates the VMOS transistors and their respective buried source regions at opposite ends of each recess. Thus, the VMOS pass gate is shared between adjacent bit lines and bit line capacitance is minimized. Also, the VMOS pass gates are self-aligned to eliminate alignment tolerances and minimize bit line capacitance. The invention also includes an efficient method for producing a semiconductor memory device with such an array of cells.
Inventors
- 👤 William R. Hiltpold
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:09
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/63; H10B; H10B12/00; H10B12/30; H10B12/34; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/512; H10D64/513; Y; Y10; Y10S; Y10S257/00; Y10S257/911
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
230 words
An integrated circuit semiconductor device having a memory core with an array of memory cells, said core compromising a substrate of crystalline silicon whose upper surface is in a <100> crystal plane; an epitaxial layer on said substrate; a series of parallel, elongated regions having the opposite conductivity from said substrate and located at spaced-apart intervals in said epitaxial layer to form bit lines; a series of buried source regions located at aligned spaced-apart locations in said substrate, spaced-below and having the same conductivity type as said elongated regions; a series of V-shaped recesses formed at spaced-apart locations between pairs of parallel bit lines, each end of each recess being contiguous with one side of a bit line, which also forms a drain region, and each end of each said recess extending downwardly into said buried source region located below said contiguous bit line; a thin gate dielectric layer covering the inner walls at both ends of each said recess; means forming a channel stopping region having the same conductivity of higher doping from said substrate and located between the ends of each said recess; gate means located on said thin dielectric layer; an insulating layer covering said epitaxial layer and said bit lines; and a plurality of conductive word line means extending generally perpendicular to said bit lines, each interconnecting said gate means of a series of aligned recesses.
Claim 2
Dependent Claim
230 words
An integrated circuit semiconductor device having a memory core with an array of memory cells, said core compromising a substrate of crystalline silicon whose upper surface is in a <100> crystal plane; an epitaxial layer on said substrate; a series of parallel, elongated regions having the opposite conductivity from said substrate and located at spaced-apart intervals in said epitaxial layer to form bit lines; a series of buried source regions located at aligned spaced-apart locations in said substrate, spaced-below and having the same conductivity type as said elongated regions; a series of V-shaped recesses formed at spaced-apart locations between pairs of parallel bit lines, each end of each recess being contiguous with one side of a bit line, which also forms a drain region, and each end of each said recess extending downwardly into said buried source region located below said contiguous bit line; a thin gate dielectric layer covering the inner walls at both ends of each said recess; means forming a channel stopping region having the same conductivity of higher doping from said substrate and located between the ends of each said recess; gate means located on said thin dielectric layer; an insulating layer covering said epitaxial layer and said bit lines; and a plurality of conductive word line means extending generally perpendicular to said bit lines, each interconnecting said gate means of a series of aligned recesses.
Claim 3
Dependent Claim
28 words
An integrated circuit device as described in claim 1 wherein said substrate is P-type conductivity material, and said drain regions and buried source areas are N-type conductivity material.
Claim 4
Dependent Claim
25 words
An integrated circuit device as described in claim 2 wherein said epitaxial layer is P-type material that is more lightly doped than said substrate material.
Claim 5
Dependent Claim
49 words
An integrated circuit device as described in claim 2 wherein each said channel stopping means comprises a diffused region of P+-type material extending into said substrate from the walls of its said recess and located transverse to the longitudinal axis of said recess near a mid-point between its ends.
Claim 6
Dependent Claim
36 words
An integrated circuit device as described in claim 1 where in the spacing between pairs of said elongated drain regions and therefore the lengths of said recesses extending between is in the range of 14-16 microns.
Claim 7
Dependent Claim
72 words
An integrated circuit device as described in claim 1 wherein the centerline of said aligned buried source regions spaced below each bit line is located approximately under the inner edge of the bit line which is contiguous with a plurality of said recesses, so that each said buried source region extends around the sidewalls of one end of each said recess; whereby the bit line capacitance for each memory cell is minimized.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-06-01 | 1984-12-01 | 1985-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-06-01 | 1988-12-01 | 1989-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-06-01 | 1992-12-01 | 1993-06-02 | $7700.00 | Window Closed / Lapsed |