US4700362A
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A-D encoder and D-A decoder system
Assignee: Dolby Laboratories Licensing Corp
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Filing: 1984-08-21
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Granted: 1987-10-13
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Expires: 2004-08-21
Abstract
Abstract An encoder converts an analog input signal to a digital signal. The encoder comprises a circuit for generating a control signal with a predetermined bandwidth from the input analog signal. The control signal indicates the desired optimum step-size to be applied in the encoder. The encoder further comprises a converter for converting the analog input signal to a digital signal. The converter is responsive to the control signal representing step-size so that the digital signal will be generated in accordance with the step-size information. Since the generation of a limited bandwidth control signal requires time, the encoder also includes a circuit for introducing time delay to the analog input signal, so that the delayed input signal reaches the converter when the control signal is available for digital encoding. A decoder generates an analog output signal from a digital signal received from an encoder through a transmission medium. The digital signal received includes a digital representation of an analog input signal to the encoder and step-size information which was used to digitally encode the analog signal in the encoder. The decoder comprises a converter responsive to a second control signal of limited bandwidth derived from the step-size information for generating from the digital representation an analog output signal. The analog output signal so generated is similar to the input analog signal.
Inventors
- 👤 Craig C. Todd
- 👤 Kenneth J. Gundry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 02:14
CPC Classifications
H; H03; H03G; H03G9/00; H03G9/005; H03G5/00; H03G5/16; H03G9/02; H03G9/025; H03M; H03M3/00; H03M3/02; H03M3/022; H04; H04B; H04B1/00; H04B1/62
Claims Analysis
Total Claims: 61
Claim 1
Independent Claim
122 words
An encoder for converting an analog input signal to a digital signal comprising: means for deriving, from the analog input signal, a control signal indicative of a desired step-size, wherein said control signal deriving means includes a bandwidth limitation circuit for limiting the bandwidth of the control signal, causing the control signal to have substantially a selected rise time; a first converter for converting said analog input signal to a digital signal, said converter responsive to said bandwidth limited control signal so that the digital signal will be generated in accordance with the desired step-size; and means for introducing time delay to said analog input signal before it reaches the first converter to compensate for the rise time of said control signal.
Claim 2
Dependent Claim
122 words
An encoder for converting an analog input signal to a digital signal comprising: means for deriving, from the analog input signal, a control signal indicative of a desired step-size, wherein said control signal deriving means includes a bandwidth limitation circuit for limiting the bandwidth of the control signal, causing the control signal to have substantially a selected rise time; a first converter for converting said analog input signal to a digital signal, said converter responsive to said bandwidth limited control signal so that the digital signal will be generated in accordance with the desired step-size; and means for introducing time delay to said analog input signal before it reaches the first converter to compensate for the rise time of said control signal.
Claim 3
Dependent Claim
23 words
The encoder of claim 1 wherein the control signal deriving means indicates the step-size required for minimum quantizing error in the first converter.
Claim 4
Dependent Claim
15 words
The encoder of claims 1 or 2, wherein the converter is an adaptive delta modulator.
Claim 5
Dependent Claim
18 words
The encoder of claim 3, wherein said adaptive delta modulator includes a leaky integrator with a cut-off frequency.
Claim 6
Dependent Claim
16 words
The encoder of claim 4, wherein said cut-off frequency is of the order of 300 Hz.
Claim 7
Dependent Claim
57 words
The encoder of claim 4 wherein the control signal deriving means is a slope detector which derives the control signal from the slopes of the signal components of the analog input signal with frequencies above the cut-off frequency and from the amplitudes of the signal components of the analog input signal with frequencies below the cut-off frequency.
Claim 8
Dependent Claim
15 words
The encoder of claim 1, wherein the control signal deriving means is a slope detector.
Claim 9
Dependent Claim
48 words
The encoder of claim 1 further comprising a second A-D converter for converting said control signal into a digital step-size information bit-stream suitable for a medium, said bit-stream being and remaining distinguishable from the digital signal when the bit-stream and the digital signal are subjected to the medium.
Claim 10
Dependent Claim
48 words
The encoder of claim 8 wherein the second A-D converter includes a D-A converter which converts said digital step-size information bit stream into an analog control signal, and wherein said first converter is responsive to said control signal in analog form derived from the step-size information bit stream.
Claim 11
Dependent Claim
21 words
The encoder of claims 8 or 9 wherein said digital step-size information bit-stream conveys a non-linear function of the desired step-size.
Claim 12
Dependent Claim
11 words
The encoder of claim 10 wherein said non-linear function is logarithmic.
Claim 13
Dependent Claim
11 words
The encoder of claim 10 wherein said non-linear function is square-root.
Claim 14
Dependent Claim
11 words
The encoder of claim 10 wherein said non-linear function is cube-root.
Claim 15
Dependent Claim
18 words
The encoder of claims 8, 11, 12 or 13 wherein said second A-D converter is a delta-sigma modulator.
Claim 16
Dependent Claim
170 words
An encoder-decoder system for converting an analog input signal to a digital signal and for generating an analog output signal from the digital signal wherein said analog output signal is similar to said analog input signal, said system comprising: means for deriving, from the analog input signal, a first control signal with a selected rise time and indicative of the desired step-size; a first converter for converting said analog input signal to the digital signal, said converter responsive to said first control signal so that the digital signal will be generated in accordance with the desired step-size; means for introducing time delay to said analog input signal before it reaches the first converter to compensate for the rise time of the first control signal; means for deriving a second control signal from the first control signal so that the second control signal is substantially similar to the first control signal; and a second converter responsive to the second control signal for generating from said digital signal the analog output signal.
Claim 17
Dependent Claim
170 words
An encoder-decoder system for converting an analog input signal to a digital signal and for generating an analog output signal from the digital signal wherein said analog output signal is similar to said analog input signal, said system comprising: means for deriving, from the analog input signal, a first control signal with a selected rise time and indicative of the desired step-size; a first converter for converting said analog input signal to the digital signal, said converter responsive to said first control signal so that the digital signal will be generated in accordance with the desired step-size; means for introducing time delay to said analog input signal before it reaches the first converter to compensate for the rise time of the first control signal; means for deriving a second control signal from the first control signal so that the second control signal is substantially similar to the first control signal; and a second converter responsive to the second control signal for generating from said digital signal the analog output signal.
Claim 18
Dependent Claim
50 words
The encoder-decoder system of claim 15 wherein said first and second control signals are in analog form, said system further comprising: means for converting said first control signal into a step-size information bit-stream suitable for a medium; and means for converging said step-size information bit-stream into said second control signal.
Claim 19
Dependent Claim
21 words
The system of claim 15 wherein the control signals generated indicate the step-size required for minimum quantizing error in the encoder.
Claim 20
Independent Claim
54 words
The system of claims 15 or 17, wherein said second converter receives said digital signal through a medium, said system further comprising a bandwidth limitation circuit for limiting the bandwidth of said second control signal to reduce the effects of errors introduced by the medium or by the conversions in the encoder or decoder.
Claim 21
Independent Claim
40 words
The system of claims 15 or 17, wherein the second control signal is derived from a step-size information bit-stream which is in turn derived from the first control signal, and wherein said step-size information bit-stream is suitable for a medium.
Claim 22
Dependent Claim
171 words
A decoder for generating an analog output signal from a digital signal received from an encoder through a medium, the digital signal including a digital representation of an analog input signal and step-size information wherein said analog input signal has been encoded in the encoder in accordance with the step-size information to provide said digital representation and wherein the step-size information is received by the decoder in advance of the corresponding digital representation of the analog signal by a predetermined and substantially fixed time interval, said decoder comprising: means for bandwidth limiting said step-size information; and a converter for converting said digital representation of an analog input signal into an output analog signal in response to the corresponding bandwidth limited step-size information, wherein said substantially fixed time interval compensates for the rise time of the bandwidth limiting means so that the bandwidth limited step-size information is available to the converter when the corresponding digital representation arrives at the converter, and wherein the effects of errors introduced by the medium are reduced.
Claim 23
Dependent Claim
171 words
A decoder for generating an analog output signal from a digital signal received from an encoder through a medium, the digital signal including a digital representation of an analog input signal and step-size information wherein said analog input signal has been encoded in the encoder in accordance with the step-size information to provide said digital representation and wherein the step-size information is received by the decoder in advance of the corresponding digital representation of the analog signal by a predetermined and substantially fixed time interval, said decoder comprising: means for bandwidth limiting said step-size information; and a converter for converting said digital representation of an analog input signal into an output analog signal in response to the corresponding bandwidth limited step-size information, wherein said substantially fixed time interval compensates for the rise time of the bandwidth limiting means so that the bandwidth limited step-size information is available to the converter when the corresponding digital representation arrives at the converter, and wherein the effects of errors introduced by the medium are reduced.
Claim 24
Dependent Claim
110 words
The decoder of claim 20, wherein the input analog signal has been encoded in the encoder in accordance with the step-size information and in response to an encoding step-size control signal and wherein the converter is responsive to the bandwidth limited step-size information in the form of a decoding step-size control signal derived from the encoding step-size control signal, and wherein the time interval has such magnitude that said decoding step-size control signal of limited bandwidth and the digital representation have a timing relationship substantially the same as that between said encoding step-size control signal and said analog input signal so that the decoding is substantially complementary to the encoding.
Claim 25
Dependent Claim
25 words
A decoder according to claim 20, wherein the bandwidth limiting means limits the step-size information to such bandwidth that said converter has substantially linear characteristics.
Claim 26
Dependent Claim
26 words
A decoder according to claim 20, wherein the bandwidth limiting means has a rise time which is substantially in the range of 5 to 20 milliseconds.
Claim 27
Dependent Claim
43 words
The decoder of claim 20, wherein said bandwidth limiting means includes a step-size information decoder for generating a step-size control signal from the step-size information, said step-size information decoder including a low pass filter for limiting the bandwidth of the step-size control signal.
Claim 28
Dependent Claim
24 words
The decoder of claim 24, wherein said low pass filter comprises three single pole filters each with a time constant of about 2 milliseconds.
Claim 29
Dependent Claim
40 words
The decoder of claim 24, wherein said step-size information is in the form of the logarithm of the slope of the analog input signal, said decoder further comprising an exponentiator for generating a slope control signal from the step-size information.
Claim 30
Dependent Claim
48 words
The decoder of claim 26, wherein said low pass filter comprises a single pole filter for filtering the output of the exponentiator and a two pole filter for filtering the step-size information and for applying the filtered step-size information to the exponentiator for generating the slope control signal.
Claim 31
Dependent Claim
48 words
The decoder of claim 26, wherein said low pass filter comprises a filter for filtering the step-size information, said filter having such a response that it restricts the ripple in its output to a few percent of its mean level, said filter applying its output to the exponentiator.
Claim 32
Dependent Claim
52 words
The decoder of claim 20, wherein said step-size information is received in the decoder in the form of digital signals by delta-sigma modulation and wherein said bandwidth limiting means comprises a low pass filter which also acts to decode the step-size information to generate a limited bandwidth step-size decoding control analog signal.
Claim 33
Dependent Claim
49 words
The decoder of claim 20, wherein said digital signal received by the decoder comprises a single bit stream where the digital representation of the analog input signal and the step-size information are received in the bit stream in a manner that allows them to be distinguished from each other.
Claim 34
Dependent Claim
24 words
The decoder of claim 20, wherein the digital representation of the analog input signal and the step-size information are received in separate bit streams.
Claim 35
Dependent Claim
15 words
A decoder according to claim 20, wherein said converter means comprises an adaptive delta demodulator.
Claim 36
Dependent Claim
37 words
The decoder of claim 20, wherein said converter comprises a delta demodulator and means for changing the level of the output analog signal as a function of the step-size control signal, for generating the analog output signal.
Claim 37
Dependent Claim
40 words
The decoder of claim 33, wherein the step-size applied by the delta demodulator is substantially fixed and wherein the level changing means applies a variable gain to the output of the delta demodulator to modulate the analog output signal level.
Claim 38
Dependent Claim
28 words
The decoder of claim 33, wherein the level changing means adjusts the step-size of the delta demodulator as a function of the step-size information received from the encoder.
Claim 39
Dependent Claim
46 words
The decoder of claim 20, wherein said converter includes a leaky integrator and a pulse height modulator responsive to the step-size information to modulate the level of the analog output signal, for generating the analog output signal from the digital representation of the analog input signal.
Claim 40
Dependent Claim
17 words
The decoder of claim 36, wherein the leaky integrator has a time constant of about 0.5 milliseconds.
Claim 41
Dependent Claim
148 words
A circuit receiving through a medium an input digital signal, a step-size control signal and a spectral control signal, said circuit for converting the input digital signal into an analog signal to provide an output analog signal and for altering the spectral content of said output analog signal, said circuit comprising: means for limiting the bandwidths of the step-size and spectral control signals; adaptive delta demodulator means for converting the input digital signal into an analog signal to provide the output analog signal in accordance with the bandwidth limited step-size control signal; and means for altering the spectral content of the output signal in accordance with the bandwidth limited spectral control signal, said step-size and spectral control signals having such limited bandwidths that substantially the same output signal is obtained irrespective of the order in which the delta demodulation and spectral altering of the input signal are performed.
Claim 42
Dependent Claim
148 words
A circuit receiving through a medium an input digital signal, a step-size control signal and a spectral control signal, said circuit for converting the input digital signal into an analog signal to provide an output analog signal and for altering the spectral content of said output analog signal, said circuit comprising: means for limiting the bandwidths of the step-size and spectral control signals; adaptive delta demodulator means for converting the input digital signal into an analog signal to provide the output analog signal in accordance with the bandwidth limited step-size control signal; and means for altering the spectral content of the output signal in accordance with the bandwidth limited spectral control signal, said step-size and spectral control signals having such limited bandwidths that substantially the same output signal is obtained irrespective of the order in which the delta demodulation and spectral altering of the input signal are performed.
Claim 43
Dependent Claim
65 words
The circuit of claim 38, wherein the delta demodulator comprises a fixed delta demodulator and a gain control which is responsive to the step-size control signal for modulating the level of the output signal, so that substantially the same output signal is obtained irrespective of the order in which three processes are performed: (a) fixed delta demodulation; (b) spectral content alteration and (c) gain control.
Claim 44
Dependent Claim
41 words
The circuit of claim 39, further comprising a fixed low pass filter for filtering the output signal, so that substantially the same output signal is obtained irrespective of the order of performing the fixed filtering together with the other three processes.
Claim 45
Dependent Claim
25 words
The encoder of claim 1, wherein said deriving means is such that the control signal has a rise time of at least about 1 millisecond.
Claim 46
Dependent Claim
238 words
An A-D encoder for use in an encoder-decoder system, said system including a decoder for generating analog output signals from digital signals received through a medium, said decoder also receiving through the medium step-size information related to the digital signals, said decoder comprising first means for bandwidth limiting said step-size information and a D-A converter for converting digital signals received into analog signals in response to the bandwidth limited step-size information related to such digital signals, said encoder comprising: means for deriving, from an analog input signal, a control signal indicative of a desired step-size; a first A-D converter for converting said analog input signal to a digital signal, said converter responsive to said control signal so that the digital signal will be generated in accordance with the desired step-size; and means for introducing time delay to said analog input signal before it reaches the first A-D converter, said time delay being such that the control signal is available to the medium by a substantially fixed time interval before the digital signal is available to the medium; wherein said substantially fixed time interval compensates for the rise time of the first bandwidth limiting means in the decoder so that the bandwidth limited step-size information is available to the D-A converter in the decoder when the digital signal related to such information arrives at such D-A converter, and wherein the effects of errors introduced by the medium are reduced.
Claim 47
Dependent Claim
238 words
An A-D encoder for use in an encoder-decoder system, said system including a decoder for generating analog output signals from digital signals received through a medium, said decoder also receiving through the medium step-size information related to the digital signals, said decoder comprising first means for bandwidth limiting said step-size information and a D-A converter for converting digital signals received into analog signals in response to the bandwidth limited step-size information related to such digital signals, said encoder comprising: means for deriving, from an analog input signal, a control signal indicative of a desired step-size; a first A-D converter for converting said analog input signal to a digital signal, said converter responsive to said control signal so that the digital signal will be generated in accordance with the desired step-size; and means for introducing time delay to said analog input signal before it reaches the first A-D converter, said time delay being such that the control signal is available to the medium by a substantially fixed time interval before the digital signal is available to the medium; wherein said substantially fixed time interval compensates for the rise time of the first bandwidth limiting means in the decoder so that the bandwidth limited step-size information is available to the D-A converter in the decoder when the digital signal related to such information arrives at such D-A converter, and wherein the effects of errors introduced by the medium are reduced.
Claim 48
Dependent Claim
24 words
The encoder of claim 42 wherein the control signal deriving means indicates the step-size required for minimum quantizing error in the first A-D converter.
Claim 49
Dependent Claim
17 words
The encoder of claims 42 or 43, wherein the first A-D converter is an adaptive delta modulator.
Claim 50
Dependent Claim
18 words
The encoder of claim 44, wherein said adaptive delta modulator includes a leaky integrator with a cut-off frequency.
Claim 51
Dependent Claim
16 words
The encoder of claim 45, wherein said cut-off frequency is of the order of 300 Hz.
Claim 52
Dependent Claim
58 words
The encoder of claim 45 wherein the control signal deriving means is a slope detector which derives the control signal from the slopes of the signal components of the analog input signal with frequencies above the cut-off frequency and from the amplitudes of the signal components of the analog input signal with frequencies below the cut off frequency.
Claim 53
Dependent Claim
15 words
The encoder of claim 42, wherein the control signal deriving means is a slope detector.
Claim 54
Dependent Claim
28 words
The encoder of claim 42 wherein said control signal deriving means includes a bandwidth limitation circuit for limiting the bandwidth of the control signal to a predetermined bandwidth.
Claim 55
Dependent Claim
48 words
The encoder of claim 42 further comprising a second A-D converter for converting said control signal into a digital step-size information bit-stream suitable for the medium, said bit-stream being and remaining distinguishable from the digital signal when the bit-stream and the digital signal are subjected to the medium.
Claim 56
Dependent Claim
50 words
The encoder of claim 50, wherein the second A-D converter includes a second D-A converter which converts the step-size information bit stream into an analog step-size control signal, and wherein said first A-D converter is responsive to said step-size control signal in analog form derived from the step-size information bit-stream.
Claim 57
Dependent Claim
21 words
The encoder of claims 50 or 51 wherein said digital step-size information bit-stream conveys a non-linear function of the desired step-size.
Claim 58
Dependent Claim
11 words
The encoder of claim 52 wherein said non-linear function is logarithmic.
Claim 59
Dependent Claim
11 words
The encoder of claim 52 wherein said non-linear function is square-root.
Claim 60
Dependent Claim
11 words
The encoder of claim 52 wherein said non-linear function is cube-root.
Claim 61
Dependent Claim
18 words
The encoder of claims 50, 53, 54 or 55 wherein said second A-D converter is a delta-sigma modulator.
References Cited (Backward Citations)
US2605361A
Cited
US2724740A
Cited
US2669608A
Cited
US2686869A
Cited
US2927962A
Cited
US2897275A
Cited
US3048781A
Cited
US3026375A
Cited
US3382438A
Cited
US3343087A
Cited
US3490045A
Cited
US3393364A
Cited
US3496468A
Cited
GB1108413A
Cited
US3497624A
Cited
US3461244A
Cited
US3518548A
Cited
US3560659A
Cited
US3500441A
Cited
US3564415A
Cited
US3568061A
Cited
US3568062A
Cited
US3609551A
Cited
US3631520A
Cited
US3699566A
Cited
US3628148A
Cited
US3823376A
Cited
US3646442A
Cited
US3621396A
Cited
US3815033A
Cited
US3706944A
Cited
US3703688A
Cited
US3727135A
Cited
US3784922A
Cited
US3745562A
Cited
DE2341381A1
Cited
US3806806A
Cited
DE2303497A1
Cited
US3857111A
Cited
US3980953A
Cited
US3973199A
Cited
US3995218A
Cited
DE2409574A1
Cited
US3916314A
Cited
US3922606A
Cited
US3913016A
Cited
US3925731A
Cited
DE2420519A1
Cited
US3918042A
Cited
US3899754A
Cited
GB1520264A
Cited
US4039949A
Cited
US3979676A
Cited
US3911363A
Cited
US4039955A
Cited
US3971987A
Cited
US3956700A
Cited
US4100493A
Cited
US4109203A
Cited
US4025852A
Cited
DE2551387A1
Cited
US4101881A
Cited
US4122300A
Cited
US4071825A
Cited
US4059800A
Cited
GB1567283A
Cited
US4215311A
Cited
US4123709A
Cited
US4151517A
Cited
US4169219A
Cited
US4110705A
Cited
US4190801B1
Cited
US4190801A
Cited
US4305050A
Cited
US4233684A
Cited
US4251804A
Cited
US4287595A
Cited
US4208740A
Cited
US4254502A
Cited
US4313204A
Cited
US4264974A
Cited
GB2076240A
Cited
US4352191A
Cited
EP0046682A1
Cited
WO1982004508A1
Cited
US4411003A
Cited
US4384278A
Cited
GB2119189A
Cited
US4507791A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1990-10-12 | 1991-04-13 | 1991-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-12 | 1995-04-13 | 1995-10-13 | $3760.00 | Window Closed / Lapsed |
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