Adaptive delta modulation information transmission system

Claim 2

In a delta-modulation system in which digital signals having two senses are employed in a first serial bit stream having a data interval between bits defined by a periodic clock signal to represent an increase or decrease of an analog signal by a predetermined amount, the combination comprising: means responsive to said first serial bit stream for providing a second serial bit stream delayed one data interval therefrom and for providing a third serial bit stream delayed two data intervals therefrom, and means receiving said first, second and third serial bit streams for providing an up count signal on a first output line when the digital signals of said first, second and third serial bit streams are equal in each of the two senses and a down count signal on a second output line when the digital signals of said first and third serial bit streams are equal to each other and not equal to the digital signal of said second serial bit stream in each of the two senses.

Claim 3

The combination of claim 1 further comprising up/down counter means responsive to said up count signal on said first output line, said down count signal on said second output line and said periodic clock signal for counting up upon receipt of an up count signal and a periodic clock signal and for counting down upon receipt of a down count signal and a periodic clock signal to provide an output representing the count in said counter means.

Claim 4

The combination of claim 2 wherein said counter means in inhibited from counting in response to an inhibit signal and the combination further comprises means for providing an inhibit signal to said counter means in alternating data intervals when an up count or down count signal is applied to said counter means in successive data intervals.

Claim 5

The combination of claim 3 further comprising decoder means receiving the count in said up/down counter means for providing a plurality of control signals in response thereto, and integrator means receiving said plurality of control signals and said first serial bit stream for integratIng a magnitude responsive to said control signals in a first direction upon receipt of a first digital signal and for integrating a magnitude responsive to said control signals in a second direction upon receipt of a second digital signal.

Claim 6

The combination of claim 4 wherein said control signals include a signal for controlling the integration time of said integrator means during a data interval.

Claim 7

In a delta-modulation system in which first and second digital signals are employed in a first serial bit stream having a data interval between bits defined by a periodic clock signal to represent an increase or decrease of an analog signal by a predetermined amount, the combination comprising: means responsive to said first serial bit stream for providing a second serial bit stream delayed one data interval therefrom and for providing a third serial bit stream delayed two data intervals therefrom, means receiving said first, second and third serial bit streams for providing an up count signal when the digital signals of said first, second and third serial bit streams are equal and a down count signal when the digital signals of said first and third serial bit streams are equal to each other and not equal to the digital signal of said second serial bit stream, up/down counter means responsive to said up count signal, said down count signal and said periodic clock signal for counting up upon receipt of an up count signal and a periodic clock signal and for counting down upon receipt of a down count signal and a periodic clock signal to provide an output representing the count in said counter means, said counter means being inhibited from counting in response to an inhibit signal, and means for providing an inhibit signal to said counter means in alternating data intervals when an up count or down count signal is applied to said counter means in successive data intervals.

Claim 8

In a delta-modulation system in which first and second digital signals are employed in a first serial bit stream having a data interval between bits defined by a periodic clock signal to represent an increase or decrease of an analog signal by a predetermined amount, the combination comprising: means responsive to said first serial bit stream for providing a second serial bit stream delayed one data interval therefrom and for providing a third serial bit stream delayed two data intervals therefrom, means receiving said first, second and third serial bit streams for providing an up count signal when the digital signals of said first, second and third serial bit streams are equal and a down count signal when the digital signals of said first and third serial bit streams are equal to each other and not equal to the digital signal of said second serial bit stream, up/down counter means responsive to said up count signal, said down count signal and said periodic clock signal for counting up upon receipt of an up count signal and a periodic clock signal and for counting down upon receipt of a down count signal and a periodic clock signal to provide an output representing the count in said counter means, said counter means being inhibited from counting in response to an inhibit signal, and means for providing an inhibit signal to said counter means in alternating data intervals when an up count or down count signal is applied to said counter means in successive data intervals.

Claim 9

The combination of claim 6 further comprising decoder means receiving the count in said up/down counter means for providing a plurality of control signals in response thereto, and integrator means receiving said plurality of control signals and said first serial bit stream for integrating a magnitude responsive to said control signals in a first direction upon receipt of a first digital signal and for integrating a magnitude responsive to said control signals in a second direction upon receipt of a second digital signal.

Claim 10

The combination of claim 7 wherein said control signals include a signal for controlling the integration time of said integrator means during a data interval.