Circuitry for generating reference signal for delta encoding systems

Claim 2

In an electrical system of the type in which a digitally encoded signal is determined at least in part by the difference between a present value of an input signal and a reference signal representative of a past value of said input signal, improved circuitry for generating said reference signal, comprising extraction means for extracting from the pattern of bits in said digitally encoded signal information relating to the time derivative of said present value to provide a corresponding control signal, said extraction means including a filter, and an envelope detector, said control signal from said extractioon means being fed to an integrating means, said integrating means being responsive to said control signal to provide said reference signal.

Claim 3

The system of claim 1 wherein said integrating means is comprised of integrating circuitry responsive to said control signal for providing said reference signal, and switching means for selecting the direction of change of said reference signal.

Claim 4

The system of claim 1 wherein said integrating means comprises integrating circuitry to provide said reference signal, said integrating circuitry having positive and negative slope control inputs controlling the direction and rate of change of said reference signal, and switching means is provided for selectively providing said control signal to said slope control inputs.

Claim 5

The system of claim 3 wherein said switching means is responsive to said encoded signal to increase or decrease said reference according to said difference between said present value and said past value.

Claim 6

The system of claim 1 further comprising modulating means for feeding back to an input of said filter a modulated signal comprising said control signal modulated by said encoded signal.

Claim 7

The system of claim 5 wherein said modulating means further comprises a selection means for selecting said input to said filter to be said modulated signal or said encoded signal.

Claim 8

The system of claim 1 whrein said extracting means further comprises a standby voltage source providing an offset to provide said control signal when said input signal is zero.

Claim 9

The system of claim 1 further comprising sampling means for providing said encoded signal, said sampling means being responsive to said input signal and said reference signal, and clock means for controlling said sampling means.

Claim 10

The system of claim 1 wherein said integrating means further comprises integrating circuitry to provide said reference signal, said integrating circuit having positive and negative slope control inputs controlling the direction and rate of change of said reference signal, and switching means being provided for selectively applying said control signal to said slope control inputs, said switching means being responsive to said encoded signal to increase or decrease said reference signal according to said difference between said present and past values of said input signal, and said extracting means further comprises modulating means for providing a modulated signal to be fed back to said input of said filter, said modulating means being responsive to said encoded signal in the manner that said modulated signal comprises said encoded amplitude modulated by said control signal, and a standby voltage sources providing an offset to provide a control signal when said input signal is zero, and said circuitry further comprises sampling means for providing said encoded signal, said sampling means responsive to said input signal and said reference signal, and clock means for controlling said sampling means.

Claim 11

The system of claim 9 wherein said clock means provides a clock output at least ten times the highest frequency of said input signal, and said filter is a low pass filter having an upper roll-off frequency of at least said highest frequency of said input signal, said envelope detector has a gain in a range of at least 1 and a hold time constant of at least the period of the lowest frequency of said input signal, and said integrating circuitry has a slew rate at the maximum value of said control signal of no more than 3 times the period of said highest frequency, said maximum value being at least the maximum amplitude of said input signal.

Claim 12

The system of claim 9 wherein said input signal has a maximum frequency of 22 KHz, said lowest frequency of 20 Hz, and said maximum amplitude of 10 volts, said clock output is at least 250 KHz, said upper roll-off frequency of said filter is at least 24 KHz, said detector has a hold time constant of at least 50 ms and a gain of at least 1.2, the maximum value of said reference is at least 10 volts, and said integrating circuitry has a slew rate of at least 0.25 v/us at said maximum control signal value and a slew rate of at least 2.5 mv/us for a value of said control signal of at least 0.1 volts.

Claim 13

The system of claim 8 wherein said clock means provides a clock output at least 10 times the highest frequency of said input signal.

Claim 14

The system of claim 12 wherein said clock output is at least 15 times the highest frequency of said input signal.

Claim 15

The system of claim 1 wherein the maximum value of said reference is at least the maximum amplitude of said input signal.

Claim 16

The system of claim 1 wherein the slew rate of said reference at the maximum value of said control signal is no greater than 3 times the period of the highest frequency of said input signal.

Claim 17

The system of claim 12 wherein said highest input frequency is 25 KHz.

Claim 18

The system of claim 13 wherein said highest input frequency is 25 KHz.

Claim 19

The system of claim 1 wherein said highest input frequency is 25 KHz.

Claim 20

The system of claim 1 wherein said period of said lowest input frequency is 50 ms.

Claim 21

The system of claim 14 wherein said maximum input signal amplitude is 10 volts.

Claim 22

The system of claim 15 wherein said period of said highest input frequency is 40μ sec.

Claim 23

The circuitry of claim 1 wherein said electrical system is a continuously variable slope delta system.

Claim 24

In an electrical system of the type in which a digitally encoded signal is determined at least in part by the difference between a present value of an input signal and a reference signal representative of a past value of said input signal, improved circuitry for generating said reference signal, comprising extraction means including a filter for extracting from the pattern of bits in said digitally encoded signal information relating to the time derivative of said present value to provide a corresponding control signal, integrating means responsive to said control signal to provide said reference signal, modulating means for feeding back to an input of said filter a modulated signal comprising said control signal modulated by said encoded signal, and means for providing as an input to said filter a mixture of said modulated signal and said digitally encoded signal, said mixture being selected to provide tracking at low slew rates between said input and the decoded output while maintaining dynamic range.

Claim 25

In an electrical system of the type in which a digitally encoded signal is determined at least in part by the difference between a present value of an input signal and a reference signal representative of a past value of said input signal, improved circuitry for generating said reference signal, comprising extraction means including a filter for extracting from the pattern of bits in said digitally encoded signal information relating to the time derivative of said present value to provide a corresponding control signal, integrating means responsive to said control signal to provide said reference signal, modulating means for feeding back to an input of said filter a modulated signal comprising said control signal modulated by said encoded signal, and means for providing as an input to said filter a mixture of said modulated signal and said digitally encoded signal, said mixture being selected to provide tracking at low slew rates between said input and the decoded output while maintaining dynamic range.

Claim 26

The system of claim 23 wherein said digitally encoded signal is from 0.03 to 3.0 percent of said mixture.

Claim 27

The system of claim 5 wherein said modulating means has a forward loop gain greater than unity, said loop gain being measured between the input to said filter and the point at which said control signal is fed back to said filter.

Claim 28

The electrical system of claim 1 wherein said filter has a cutoff frequency selected to be at least the highest frequency of the input signal.

Claim 29

The electrical system of claim 1 wherein said envelope detector includes means producing a rectified control signal that rises rapidly, to follow increases in the filter output, and decays more slowly than it rises upon decreases in the filter output.

Claim 30

The system of claim 27 wherein the speed of decay of said means producing a rectified control signal is determined by a hold time constant that is selected to be long enough to make quantization noise less audible.

Claim 31

The electrical system of claim 28 wherein said hold time constant is selected to be longer than the period of the lowest frequency of the input signal.