Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
234 words
A continuously variable sloped delta modulator for voice frequency signals comprising: a source of analog input signals within the voice frequency range, said modulator including a comparator for producing binary signals derived from said analog input signals, means coupling said source to one input of said comparator, a network for reconstructing an analog based on said binary signals, and a feedback path between said network and a second input to said comparator for comparison with said analog input signal to produce a modulator output signal, said reconstructing network including, a multiple bit shift register for storing successive binary signals received from said comparator, a first output from said register indicative of the binary signal most recently received by said register from said comparator, an output signal path from said modulator for transmitting an output indicative of said most recently received binary signal, a multiple input ladder attenuator network receptive of successive signals in parallel clocked from said shift register, said attenuator network operative to sum and weight signals received from said register and for delivering successive signals for feedback, first means for integrating successive signals received from said attenuator network, second integrating means productive of an amplitude envelope signal based on the slope of the signal received from the first integrating means, and a first and a second bypass path coupling said register first output path into said feedback path bypassing said attenuator network.
Claim 2
Dependent Claim
234 words
A continuously variable sloped delta modulator for voice frequency signals comprising: a source of analog input signals within the voice frequency range, said modulator including a comparator for producing binary signals derived from said analog input signals, means coupling said source to one input of said comparator, a network for reconstructing an analog based on said binary signals, and a feedback path between said network and a second input to said comparator for comparison with said analog input signal to produce a modulator output signal, said reconstructing network including, a multiple bit shift register for storing successive binary signals received from said comparator, a first output from said register indicative of the binary signal most recently received by said register from said comparator, an output signal path from said modulator for transmitting an output indicative of said most recently received binary signal, a multiple input ladder attenuator network receptive of successive signals in parallel clocked from said shift register, said attenuator network operative to sum and weight signals received from said register and for delivering successive signals for feedback, first means for integrating successive signals received from said attenuator network, second integrating means productive of an amplitude envelope signal based on the slope of the signal received from the first integrating means, and a first and a second bypass path coupling said register first output path into said feedback path bypassing said attenuator network.
Claim 3
Dependent Claim
62 words
A modulator as claimed in claim 1, wherein there is a second comparator interposed between said first and second integrating means, and means coupling said register first output to respective inputs of said second comparator by said first and second bypass paths, respectively, for comparing the successive outputs of said first integrating means with successive binary input signals received from said register.
Claim 4
Dependent Claim
93 words
A modulator as claimed in claim 2, wherein said second comparator includes two inputs, means coupling each of said last-mentioned inputs to an output of said first integrating means, and each second comparator input also coupled, respectively, to said first and second bypass paths, means in said first bypass path to one input to said second comparator for inverting the polarity of a digital signal being fed to said second comparator to switch the output of the first integrating means to the other input to said comparator during the receipt of said signal.