Patent US2559279A successfully refreshed from Google Patents.
← Back to Patent Explorer
US3706944A Expired / Lapsed US ⏱️ 0.0 years remaining

Discrete adaptive delta modulator

Assignee: AT&T Inc
•
Filing: 1970-12-02
•
Granted: 1972-12-19
•
Expires: 1990-12-02
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A discrete adaptive delta modulator (DADM) comprising a comparator, a quantizer and a sampling pulse generator operating at the rate f2 is characterized in that complex analog feedback circuitry is replaced by a programmable pulse generator operating at the rate ft, which provides a controlled number of pulses k during each sampling period 1/f2 to a single step-size analog feedback integrator. The number of pulses k provided by the programmable generator multiplied by the basic step size sigma o of the feedback integrator determines the step-size sigma k in the feedback signal. This DADM is readily implemented in integrated circuit form and retains such advantages of the nonadaptive delta modulator as circuit simplicity and the requirement of only a single adjustable basic step size sigma o. The number n of available step sizes sigma k, which is determined by the ratio of the generator rates ft and fs, can be several hundred compared to a maximum of ten in a conventional DADM.

Inventors

  • 👤 Stuart Keene Tewksbury

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 08:04
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/02; H03M3/022

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 99 words
A delta modulator for converting an analog input signal into a digital output signal comprising: comparator means jointly responsive to said analog input signal and a feedback signal for producing a difference signal, means for generating sampling pulses at the rate fs, means jointly responsive to said difference signal and said sampling pulses at the rate fs for producing said digital output signal, means for generating pulses at the rate ft greater than or equal to fs, and integrating means jointly responsive to said digital output signal and said pulses at the rate ft for producing said feedback signal.
Claim 2
Dependent Claim 99 words
A delta modulator for converting an analog input signal into a digital output signal comprising: comparator means jointly responsive to said analog input signal and a feedback signal for producing a difference signal, means for generating sampling pulses at the rate fs, means jointly responsive to said difference signal and said sampling pulses at the rate fs for producing said digital output signal, means for generating pulses at the rate ft greater than or equal to fs, and integrating means jointly responsive to said digital output signal and said pulses at the rate ft for producing said feedback signal.
Claim 3
Dependent Claim 41 words
The delta modulator of claim 1 wherein said digital output signal producing means is a two-level quantizer which emits a first output pulse when said difference signal is positive and emits a second output pulse when said difference signal is negative.
Claim 4
Dependent Claim 13 words
The delta modulator of claim 2 wherein said two-level quantizer is a flip-flop.
Claim 5
Dependent Claim 23 words
The delta modulator of claim 1 wherein said means for generating pulses at the rate ft is responsive to said digital output signal.
Claim 6
Dependent Claim 60 words
The delta modulator of claim 1 wherein said integrating means is a single step-size analog integrator having the basic step size sigma 0 and wherein amplitude changes sigma k in the feedback signal during any sampling interval 1/fs are given by the product of sigma 0 and the number of pulses k applied at the rate ft to said integrator.
Claim 7
Dependent Claim 17 words
The delta modulator of claim 5 wherein said single step-size analog integrator is a charge parcelling integrator.
Claim 8
Dependent Claim 30 words
The delta modulator of claim 5 wherein said means for generating pulses at the rate ft is responsive to said means for generating sampling pulses at the constant rate fs.
Claim 9
Dependent Claim 89 words
The delta modulator of claim 5 wherein said means for generating pulses at the rate ft further comprises: counter means, adaption logic responsive to said digital output signal for controlling the count of said counter means, a clock source for generaTing pulses at the constant rate ft max greater than or equal to ft, and pulse rate selecting means jointly responsive to said clock source and said counter means for emitting at the rate ft said number of pulses k numerically equal to the count of said counter means.
Claim 10
Dependent Claim 34 words
The delta modulator of claim 8 wherein said pulse rate selecting means is a binary rate multiplier for producing during the interval 1/fs said k pulses ranging in number from 1 to ft max/fs.
Claim 11
Dependent Claim 25 words
The delta modulator of claim 8 wherein said counter is a binary counter whose count varies from 1 to ft max/fs in powers of 2.
Claim 12
Dependent Claim 32 words
The delta modulator of claim 8 wherein said means for generating sampling pulses at the rate fs is responsive to said clock source which generates pulses at the constant rate ft max.
Claim 13
Dependent Claim 19 words
The delta modulator of claim 5 wherein said sampling pulse generating means is responsive to said digital output signal.
Claim 14
Dependent Claim 89 words
The delta modulator of claim 12 wherein said means for generating sampling pulses at the rate fs further comprises: counter means, adaption logic responsive to said digital output signal for controlling the count of said counter means, a clock source for generating pulses at the constant rate fs max greater than or equal to fs, and pulse rate selecting means jointly controlled by said clock source and said counter means for emitting at the rate fs a plurality of pulses numerically equal to the count of said counter means.

References Cited (Backward Citations)

US3273141A Cited
US3270335A Cited
US3461244A Cited
US3497624A Cited
US3500441A Cited
US3609551A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-12-19 1976-06-19 1976-12-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-12-19 1980-06-19 1980-12-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-12-19 1984-06-19 1984-12-19 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag