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US3757252A
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Digital companded delta modulator
Assignee: Université de Sherbrooke
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Filing: 1971-12-13
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Granted: 1973-09-04
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Expires: 1991-12-13
Abstract
Abstract A digital companded delta modulator comprising a comparator having a first input connected to receive an input analog signal, a second input obtained from an integrator located in the conventional feedback loop of the delta modulator, and pulse generating means connected to the output of the comparator and responsive to a clock for generating a binary pulse of one polarity or the other as determined by the comparator. A binary up and down counter is connected to the pulse generating means through a control circuit which makes the decision as to whether an up count a down count or no count at all is required. The output of the counter is applied to a decoder for converting the binary output of the up and down counter into a number of decimal outputs. An amplifier having a corresponding number of values of gains is connected to the output of the decoder and is thus responsive to the level of the up and down counter for providing a predetermined gain into the feedback loop of the delta modulator. The integrator is connected to the output of the amplifier and its output is connected to the comparator which compares the output signal of the integrator with the input analog signal and generates a signal depending upon the difference between the two signals.
Inventors
- 👤 M Villeret
- 👤 P Deschenes
- 👤 M Richetin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:13
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/02; H03M3/022
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
185 words
A digital companded delta modulator comprising: a. a comparator having a first and a second input and a single output, said first input being connected to receive an input analog signal; b. a clock; c. pulse generating means connected to the output of said comparator and responsive to said clock for generating binary pulses; d. a binary up and down counter having a binary output; e. a control circuit interconnecting said pulse generating means and said up and down counter, said control circuit making the decision as to whether an up count, a down count or no count at all is required; f. a decoder for converting the binary output of said up and down counter into a number of decimal outputs; g. amplifying means having a corresponding number of values of gains connected to said decoder outputs; and h. an integrator connected to said amplifier and having an output connected to said second input of said comparator, whereby said comparator compares the output signal of said integrator with the input analog signal and generates a signal depending on the difference between the two signals.
Claim 2
Dependent Claim
185 words
A digital companded delta modulator comprising: a. a comparator having a first and a second input and a single output, said first input being connected to receive an input analog signal; b. a clock; c. pulse generating means connected to the output of said comparator and responsive to said clock for generating binary pulses; d. a binary up and down counter having a binary output; e. a control circuit interconnecting said pulse generating means and said up and down counter, said control circuit making the decision as to whether an up count, a down count or no count at all is required; f. a decoder for converting the binary output of said up and down counter into a number of decimal outputs; g. amplifying means having a corresponding number of values of gains connected to said decoder outputs; and h. an integrator connected to said amplifier and having an output connected to said second input of said comparator, whereby said comparator compares the output signal of said integrator with the input analog signal and generates a signal depending on the difference between the two signals.
Claim 3
Dependent Claim
32 words
A digital companded delta modulator as defined in claim 1, wherein said pulse generating means comprises a first flip-flop for storing output pulses of said comparator, said flip-flop having an output terminal.
Claim 4
Dependent Claim
79 words
A digital companded delta modulator as defined in claim 2, wherein said control circuit includes a second flip-flop connected to the output terminal of said first flip-flop and responsive to said clock for storing the preceding output pulse of said comparator, said control circuit being responsive to said first and second flip-flops and to the actual state of the counter for providing control signals to the counter for an up count, a down count or no count at all.
Claim 5
Dependent Claim
73 words
A digital companded delta modulator as defined in claim 3, wherein the portion of control circuit providing the no count signal includes means responsive to the lowest and highest output of said decoder for disabling the operation of the counter when the lowest value of the counter has been reached and a down count signal occurs and when the highest level of the counter has been reached and an up count signal occurs.
Claim 6
Dependent Claim
38 words
A digital companded delta modulator as defined in claim 1, wherein the decoder has eight decimal outputs and wherein the amplying means includes eight positive and eight negative values of gains controlled by corresponding outputs of said decoder.
Claim 7
Dependent Claim
38 words
A digital companded delta modulator as defined in claim 5, further comprising gate means connected to said pulse generating means and tO said decoder for operating the corresponding positive or negative values of gains of said amplying means.
Claim 8
Dependent Claim
99 words
A digital companded delta modulator as defined in claim 3, wherein said clock includes an oscillator generating a square wave output and three one-shot circuits responsive to said oscillator for generating three pulses shifted with respect to each other, the first pulse corresponding to the leading edge of the square wave and controlling the operation of the first flip-flop the second pulse occurring a predetermined time interval later and controlling the operation of the up and down counter, and the third pulse corresponding to the trailing edge of the square wave and controlling the operation of said control circuit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-03 | 1977-03-05 | 1977-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-03 | 1981-03-05 | 1981-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-03 | 1985-03-05 | 1985-09-04 | $7700.00 | Window Closed / Lapsed |