Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
306 words
An instantaneous adaptative delta modulator comprising; a. a comparator having a first and a second input and a single output, said first input being connected to receive an input analog signal; b. a shift register connected to the output of said comparator for storing the digit generated at sampling time T0 and the digits generated at sampling times T 1 and T 2; c. a binary up and down counter; d. a control circuit interconnecting said shift register and said up and down counter, said control circuit comprising first gate means and second gate means responsive to a combination of the digits generated at sampling times T0, T 1 and T 2 for making the decision as to whether an up count, a down count, or no count is required depending on the digits stored into the shift register and on the actual state of the up and down counter; e. a logic circuit having a plurality of outputs for selecting and producing a signal on one of said outputs in response to the binary output of said up and down counter, all of said outputs except the selected one being open-circuited; f. a plurality of resistive elements, each being connected to one output of said plurality of outputs of said logic circuit, said elements weighing the logic circuit output signal; g. an amplifier connected in series with said plurality of resistive elements and thus responsive to said up and down counter for providing a predetermined gain corresponding to the logic output signal weighed by the selected resistive element; h. an integrator connected to said amplifier and having an output connected to said second input of the comparator; whereby said comparator compares the output signal of said integrator with the input analog signal and generates a signal depending on the difference between the two input signals.
Claim 2
Dependent Claim
306 words
An instantaneous adaptative delta modulator comprising; a. a comparator having a first and a second input and a single output, said first input being connected to receive an input analog signal; b. a shift register connected to the output of said comparator for storing the digit generated at sampling time T0 and the digits generated at sampling times T 1 and T 2; c. a binary up and down counter; d. a control circuit interconnecting said shift register and said up and down counter, said control circuit comprising first gate means and second gate means responsive to a combination of the digits generated at sampling times T0, T 1 and T 2 for making the decision as to whether an up count, a down count, or no count is required depending on the digits stored into the shift register and on the actual state of the up and down counter; e. a logic circuit having a plurality of outputs for selecting and producing a signal on one of said outputs in response to the binary output of said up and down counter, all of said outputs except the selected one being open-circuited; f. a plurality of resistive elements, each being connected to one output of said plurality of outputs of said logic circuit, said elements weighing the logic circuit output signal; g. an amplifier connected in series with said plurality of resistive elements and thus responsive to said up and down counter for providing a predetermined gain corresponding to the logic output signal weighed by the selected resistive element; h. an integrator connected to said amplifier and having an output connected to said second input of the comparator; whereby said comparator compares the output signal of said integrator with the input analog signal and generates a signal depending on the difference between the two input signals.
Claim 3
Dependent Claim
34 words
A modulator as defined in claim 1, wherein said shift register has at least three memory units so as to permit storage of the digits generated at times T0, T 1 and T 2.
Claim 4
Dependent Claim
138 words
A modulator as defined in claim 1, wherein said first gate means is responsive to the presence of three identical digits in the shift register to feed an up count signal to the up and down counter, and to the presence of non-identical digits in the shift register to feed a down count signal to the up and down counter, and said second gate mEans is responsive to the lowest and highest state of said logic circuit for disabling the operation of the up and down counter when the lowest value of the logic circuit has been reached and that a down count signal is fed to the up and down counter, and when the highest value of the logic circuit has been reached and that an up count signal is fed to the up and down counter.
Claim 5
Dependent Claim
38 words
A modulator as defined in claim 1, wherein the number of outputs of said logic circuit is six of two different polarities thus permitting to said amplifier to have six different values of gain and their corresponding polarities.
Claim 6
Dependent Claim
23 words
A modulator as defined in claim 4, wherein the number of gains n is different from 6, namely n > or = 4.