Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
162 words
In a delta modulation system including an analog input connected to a first input of an analog signal compare means whose output in turn is connected to a periodic sampling means generating a delta modulated signal d i at a sampling frequency which is provided to a system output and to the input of a companding means whose companded signal output α i is connected through an integrating network means to a reconstructed analog signal input, wherein said companding means further comprises: a digital switching circuit for calculating α.sub.i ={(C-B)α.sub.i-1 } when d.sub.i ≠d.sub.i-1, α.sub.i ={(A+C)α.sub.i-1 } when d.sub.i =d.sub.i-1, and ##EQU3## when d.sub.i =d.sub.i-1 =. . . =d.sub.o for i>2 where A, B, C are positive constants less than unity A+C > unity C-B<unity, and α i for i=0 is the minimum step size generated by said companding means; whereby rapid adaptive digital companding of the delta modulation signal fed back via said integrating network to said compare means is achieved.
Claim 2
Dependent Claim
162 words
In a delta modulation system including an analog input connected to a first input of an analog signal compare means whose output in turn is connected to a periodic sampling means generating a delta modulated signal d i at a sampling frequency which is provided to a system output and to the input of a companding means whose companded signal output α i is connected through an integrating network means to a reconstructed analog signal input, wherein said companding means further comprises: a digital switching circuit for calculating α.sub.i ={(C-B)α.sub.i-1 } when d.sub.i ≠d.sub.i-1, α.sub.i ={(A+C)α.sub.i-1 } when d.sub.i =d.sub.i-1, and ##EQU3## when d.sub.i =d.sub.i-1 =. . . =d.sub.o for i>2 where A, B, C are positive constants less than unity A+C > unity C-B<unity, and α i for i=0 is the minimum step size generated by said companding means; whereby rapid adaptive digital companding of the delta modulation signal fed back via said integrating network to said compare means is achieved.
Claim 3
Dependent Claim
167 words
The delta modulation system of claim 1, wherein said companding means further comprises: a delay means connected between said input of said companding means and a delay node; an inverted exclusive OR gate having first and second inputs connected to said input of said companding means and said delay node, respectively, for generating an output signal when d i =d i-1 ; a first arithmetic means having a control input connected to said output of said inverted exclusive OR gate and a feedback input connected to said companded signal output, for calculating ##EQU4## a second arithmetic means having a first input connected to the output of said first arithmetic means, a feedback input connected to said companded signal output and an output connected to said compandor output, for calculating the product C α i-1 , adding it to said calculated value of ρ i and outputting the sum as α i when d i =d i-1 =d i-2 =d i-3 . . . (alike bits > 3).
Claim 4
Dependent Claim
118 words
The delta modulation system of claim 2, wherein said companding means further comprises: an exclusive OR gate having first and second inputs connected to said input of said companding means and said delay node, for generating an output signal when d i ≠d i-1 ; a third arithmetic means having a control input connected to said output of said exclusive OR gate, a feedback input connected to said companded signal output and an output connected to a third input of said second arithmetic means, for calculating the value of the product B α i-1 ; said second arithmetic means calculating the value (C-B) α i-1 and outputting that value as α i when d i ≠d i-1 .
Claim 5
Dependent Claim
28 words
The delta modulation system of claim 3, which further comprises a minimum step size circuit having a well behaved idle pattern and a selective build-up in step size.
Claim 6
Dependent Claim
317 words
The delta modulation system of claim 3, which further comprises: a time division analog signal multiplexor connected between a plurality of M analog input signal lines and said first input of said analog signal compare means, having a control input connected to a scan clock, for cyclically connecting each of said M input signal lines to said first input of said compare means under control of said scan clock; a first storage means connected to said output of said first arithmetic means, having a control input connected to said scan clock, for cyclically storing and accessing stored values of ρ i for each of said corresponding M input signal lines, under control of said scan clock; a second storage means connected to said output of said second arithmetic means, having a control input connected to said scan clock, for cyclically storing and accessing stored values of α i for each of said corresponding M input signal lines, under control of said scan clock; said integrating network means being a digital filter for converting the companded delta modulated signal output from said companding means, corresponding to each of said M input signal lines; a digital amplitude storage means connected to an output of said filter means, having a control input connected to said scan clock, for cyclically storing and accessing stored values of said digitized reconstructed analog signal output from said filter means for each of said corresponding M input signal lines, under control of said scan clock; a digital-to-analog converter connected between said digitized amplitude storage means and said reconstructed analog signal input of said analog signal compare means to enable the comparison by said compare means of the analog signal corresponding to that one of said plurality of multiplexor inputs connected to said first input of said compare means; whereby a plurality of analog input signals may be delta modulated with a minimum amount of hardware.
Claim 7
Dependent Claim
20 words
The delta modulation system of claim 5, wherein time division multiplexing of both M-input and M-output analog signals is achieved.