Digital transmission system with frequency weighted noise reduction

Claim 2

In a digital transmission system an encoder for converting an input analog signal into an output digital code, comprising: means for obtaining a present and (N-1) future samples of said input analog signal at a particular sampling rate, where N is an integer; means for generating an analog equivalent signal from the output digital code, the analog equivalent signal being an analog replica of the output digital code; means for generating quantizing error terms based upon the difference between the analog equivalent signal of the digital code and the present sample of the input analog signal; means for storing M successive previously generated quantizing error terms; and means for quantizing the present and (N-1) future samples of the input analog signal into the digital code according to a plurality of quantizing regions, which produce a reduced frequency weighted quantizing error, said means for quantizing including means for varying the quantizing regions to correct for quantizing errors as indicated by the M successive previously generated quantizing error terms, and means for encoding the quantized signals.

Claim 3

A digital encoDer for converting an input analog signal into a digital code comprising: means for obtaining a present and (N-1) future samples of said input analog signal at a particular sampling rate; a plurality of summing means for combining each sample with a separate feedback signal; quantizing means responsive to the outputs of said plurality of summing means for simultaneously generating the combination of bits of the digital code, representing the present and (N-1) future samples of the input analog signal; means for generating an analog equivalent signal from the bits of the digital code; means for generating quantizing error terms by computing the difference between the analog equivalent signal of the digital code and the present sample of the input analog signal; means responsive to the present and previously generated quantizing error terms for generating the separate feedback signals, the feedback signals being generated in such a way as to allow the quantizing means to generate the digital code which produces a reduced frequency weighted quantizing error according to a noise penalty function when taken together with the present and previously generated quantizing error terms.

Claim 4

A digital encoDer for converting an input analog signal into a digital code comprising: means for obtaining a present and (N-1) future samples of said input analog signal at a particular sampling rate; a plurality of summing means for combining each sample with a separate feedback signal; quantizing means responsive to the outputs of said plurality of summing means for simultaneously generating the combination of bits of the digital code, representing the present and (N-1) future samples of the input analog signal; means for generating an analog equivalent signal from the bits of the digital code; means for generating quantizing error terms by computing the difference between the analog equivalent signal of the digital code and the present sample of the input analog signal; means responsive to the present and previously generated quantizing error terms for generating the separate feedback signals, the feedback signals being generated in such a way as to allow the quantizing means to generate the digital code which produces a reduced frequency weighted quantizing error according to a noise penalty function when taken together with the present and previously generated quantizing error terms.

Claim 5

An encoder as claimed in claim 2 wherein said means for obtaining a present and (N-1) future samples of said input analog signal comprises: means for sampling the amplitude of the input signal and holding the sample for a period of time; and means for storing the shifting at the sampling rate a plurality of successive samples of the input signal, the earliest stored sample being considered the present sample and all subsequent samples being considered future samples.

Claim 6

An encoder as claimed in claim 2 wherein said quantizing means comprises means for determining in which of a plurality of encoding regions the combination of outputs from said summing means belongs and generating digital bits for the output code which represent that region.

Claim 7

An encoder as claimed in claim 4 wherein the boundary between encoding regions is determined by the equation (Se - Si)T BN Sf + (Se - Si)T Beta Qp 1/2 (Se - Si)T BN(Se + Si), with Se being the analog reconstruction of the digital bits representing one region, Si being the analog reconstruction of the digital bits representing another region, BN and Beta being segments of a matrix B describing the frequency weighting, Qp being the vector of past quantizing error terms, and T indicating the transpose of the indicated matrix.

Claim 8

An encoder as claimed in claim 5, wherein the matrix B in partition form is given by

Claim 9

An encoder as claimed in claim 6 wherein said means for generating the separate feedback signals comprises: means for storing and shifting at the sampling rate a plurality of quantizing error terms; means for multiplying the stored quantizing error terms by coefficients of the B matrix and generating partial products by summing the results; and means for combining the partial products to produce the feedback terms psi such that psi BN 1 Beta Qp.

Claim 10

An encoder as claimed in claim 7 wherein said means for storing and shifting comprises an analog shift register.

Claim 11

An encoder as claimed in claim 7 wherein said means for storing and shifting comprises a plurality of means for delaying the present error terms for a plurality of successive sampling periods.

Claim 12

An encoder as claimed in claim 2 wherein said encoder is arranged to function as a delta modulator by further including means for subtracting the output of said means for generating an analog equivalent signal from the present and future samples of the input signal.

Claim 13

An encoder as claimed in claim 10 wherein said means for generating an analog equivalent signal comprises: a digital shift register having a plurality of stages, the output bits of the quantizing means being uniformly loaded in parallel into the stages of said shift digital register, the first bit of the code being loaded into the last stage of said digital shift register and the last bit of the code being loaded into the first stage of said digital shift register; and means for integrating impulses generated in response to the bits stored in said digital shift register as they are shifted into the last stage of said digital shift register.

Claim 14

A digital encoder for converting an input analog signal into a digital code comprising: means for obtaining a present and (N-1) successive future samples of said input analog signal; N quantizing means for sequentially generating the output code, the first quantizing means generating the first bit of the code in response to a first partial feedback signal, the present sample, and the (N-1) future samples, the succeeding quantizing means each generating a succeeding bit of the code in response to succeeding separate partial feedback signals and one less sample than the preceding quantizing means, the one less sample being the one least in the future, the Nth of said quantizing means generating the last bit of the code in response to a last partial feedback signal and the most future sample; means for sequentially collecting the output bits of said N quantizing means and generating an analog equivalent signal in response to the bits; means for generating quantizing error terms by computing the difference between the analog equivalent signal of the digital code during the time a bit is generated and the sample of the input analog signal used in the generation of that bit which is the one least in the future; and means responsive to the present and previously generated quantizing error terms for generating the separate partial feedback signals, the partial feedback signals being generated in such a way as to allow each of the N quantizing means to generate a digital bit of the output digital code which produces a reduced frequency weighted quantizing error according to a noise penalty function when taken together with previously generated quantizing error terms.

Claim 15

A digital encoder for converting an input analog signal into a digital code comprising: means for obtaining a present and (N-1) successive future samples of said input analog signal; N quantizing means for sequentially generating the output code, the first quantizing means generating the first bit of the code in response to a first partial feedback signal, the present sample, and the (N-1) future samples, the succeeding quantizing means each generating a succeeding bit of the code in response to succeeding separate partial feedback signals and one less sample than the preceding quantizing means, the one less sample being the one least in the future, the Nth of said quantizing means generating the last bit of the code in response to a last partial feedback signal and the most future sample; means for sequentially collecting the output bits of said N quantizing means and generating an analog equivalent signal in response to the bits; means for generating quantizing error terms by computing the difference between the analog equivalent signal of the digital code during the time a bit is generated and the sample of the input analog signal used in the generation of that bit which is the one least in the future; and means responsive to the present and previously generated quantizing error terms for generating the separate partial feedback signals, the partial feedback signals being generated in such a way as to allow each of the N quantizing means to generate a digital bit of the output digital code which produces a reduced frequency weighted quantizing error according to a noise penalty function when taken together with previously generated quantizing error terms.

Claim 16

A digital encoder as claimed in claim 12 wherein each of said N quantizing means comprises: a plurality of comparison means for comparing all possible pairs of one and zero analog equivalent signals for a particular quantizer with the combination of inputs to said particular quantizer and generating an internal ''''1'''' bit if the input combination is closer to the one analog equivalent signal than to the zero analog equivalent signal, and an internal ''''0'''' bit if it is not, said one analog equivalent signals being those analog equivalent signals of digital codes having a ''''1'''' as the first bit, said zero analog equivalent signals being those analog equivalent signals of digital codes having a ''''0'''' as the first bit; and means for logically combining the internal bits of said plurality of comparison means to determine if the combination of inputs to a particular quantizing meAns is closer to a particular one analog equivalent signal than to any zero analog equivalent signal and generating a ''''1'''' output bit for said particular quantizing means if it is and a ''''0'''' output bit if it is not.

Claim 17

A digital encoder as claimed in claim 13 wherein said comparison means comprises circuit means for determining if the input combination is closer to the one analog equivalent signals than to the zero analog equivalent signals according to the expression: (Sl - Si)TBN Sf + (Sl - Si)T Sigma - 1/2 (S - Si)TBN (Sl + Si) > 0, Si being one of the one analog equivalent signals, Sl being one of the zero analog equivalent signals, Sf being the combination of inputs to said particular quantizing means, Sigma being the partial feedback term for said particular quantizing means, BN being a segment of weighting matrix B determined by the noise penalty function, T indicating the transpose of the indicated matrix, and a positive result for the expression indicating that the input combination is closer to Sl than to Si.

Claim 18

A digital encoder as claimed in claim 14 wherein said partial feedback terms are given by the matrix Sigma Beta Qp.