← Back to Patent Explorer
US4110705A Expired / Lapsed US ⏱️ 0.0 years remaining

Noise reduction method and apparatus for companded delta modulators

Assignee: International Business Machines Corp
•
Filing: 1977-10-17
•
Granted: 1978-08-29
•
Expires: 1997-10-17
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A noise reduction circuit and method are described for implementation in a delta modulation system for signal transmission. Under certain conditions when the delta modulator has selected the minimum step size for encoding and transmission, the present technique and apparatus are effective to change the minimum step size in a way which prevents low level noise generation from occurring in the delta modulation system. The technique and circuit can be utilized with most commonly available delta modulators which have means for changing the step size (i.e., the delta) but is used to the best effect on more stable implementations of delta modulators where an integrator is replaced by a digital accumulator and a digital-to-analog converter.

Inventors

  • 👤 William G. Crouse

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 15:12
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/02; H03M3/022

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 137 words
In a delta modulation digital signal transmission system having a voltage step size generator operating under a simulation algorithm for controlling the generation of 1 and 0 bits in the transmission system for later demodulation and reconstruction of an analog waveform, the method of reducing random or low level noise production during low level or quiet passages of the analog input signal comprising steps of: detecting the minimum step size calculation at the output of the step size generator; comparing the presently modulated digital bit to be transmitted with the previously transmitted digital bit; and when said bits do not compare and said minimum step size has been detected, modifying the calculated step size by forcing the step size for the bit next transmitted to be greater than the minimum step size used in the modulation system.
Claim 2
Dependent Claim 137 words
In a delta modulation digital signal transmission system having a voltage step size generator operating under a simulation algorithm for controlling the generation of 1 and 0 bits in the transmission system for later demodulation and reconstruction of an analog waveform, the method of reducing random or low level noise production during low level or quiet passages of the analog input signal comprising steps of: detecting the minimum step size calculation at the output of the step size generator; comparing the presently modulated digital bit to be transmitted with the previously transmitted digital bit; and when said bits do not compare and said minimum step size has been detected, modifying the calculated step size by forcing the step size for the bit next transmitted to be greater than the minimum step size used in the modulation system.
Claim 3
Dependent Claim 23 words
A method as described in claim 1 wherein: said modified step size is twice the minimum step size used in said modulation system.

References Cited (Backward Citations)

US3716803A Cited
US3806806A Cited
US3995218A Cited
US4025852A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-08-28 1982-02-27 1982-08-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-08-28 1986-02-27 1986-08-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-08-28 1990-02-27 1990-08-29 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag