Demultiplexer for two-stage framing

Claim 1

Apparatus for determining the relative location of framing bits in an incoming digital signal, which framing bits recur at intervals of I bits and form a first recurring predetermined bit sequence, which apparatus comprises: means for generating a clock signal in response to the incoming digital signal, the clock signal having pulses corresponding to bits in the incoming digital signal; a storage device having I storage locations, each of which locations can store L bits; addressing means for addressing consecutive locations in the storage device in response to pulses of the clock signal, the consecutive storage locations wrapping around to the first after the Ith storage location has been reached; storing means, responsive to the output of the addressing means, the clock signal and the incoming digital signal, for (a) addressing a location in the storage device, (b) retrieving the bits stored therein, (c) discarding the bit stored therein for the longest period of time, (d) forming a result with the remaining L-1 bits and a bit from the incoming digital signal, and storing th result in the addressed location; and examination means for examining the result for equivalence with an L bit code which represents a portion of the pre-determined sequence and for providing a signal when equivalence is found, whereby the storage location at which bits from the pre-determined bit sequence are stored and thereby the relative location of framing bits forming the sequence is determined.

Claim 17

An apparatus for demultiplexing an incoming digital signal which has an input clock rate, control bit intervals recurring every R bits, the first bit of the control bit interval being a control bit which is followed by R-1 information bits from several signals, some of which control bits are stuff indicator bits which indicate the presence of stuff bits in the R-1 information bits, which apparatus comprises: means responsive to the incoming digital signal, for generating pulses at a higher clock rate tha the input clock rate, counter means, responsive to the pulses, for counting the higher clock rate pulses occurring in a control bit interval, means, responsive to the incoming digital signal, for decoding the stuff indicators to identify stuff bits in the subsequent information bits, means, responsive to the higher clock rate pulses, output from the stuff identifier means, and output from the counter means, for deleting pulses from the higher clock rate pulses at various values of the count of the counter means to provide the output clocks.

Claim 18

An apparatus for demultiplexing an incoming digital signal which has an input clock rate, control bit intervals recurring every R bits, the first bit of the control bit interval being a control bit which is followed by R-1 information bits from several signals, some of which control bits are stuff indicator bits which indicate the presence of stuff bits in the R-1 information bits, which apparatus comprises: means responsive to the incoming digital signal, for generating pulses at a higher clock rate tha the input clock rate, counter means, responsive to the pulses, for counting the higher clock rate pulses occurring in a control bit interval, means, responsive to the incoming digital signal, for decoding the stuff indicators to identify stuff bits in the subsequent information bits, means, responsive to the higher clock rate pulses, output from the stuff identifier means, and output from the counter means, for deleting pulses from the higher clock rate pulses at various values of the count of the counter means to provide the output clocks.