Frame synchronization system for digital multiplexing systems

Claim 2

A frame synchronizing system for a demultiplexer of a digital multiplexing system wherein a frame sync pattern is a pseudorandom (PN) sequence of bits, said system comprising a. a PN sequence generator for generating a serial PN bit sequence as a function of input data to said demultiplexer, b. means for storing successive pluralities of sequential bits of said input data, c. means for sequentially comparing the bits of said input data with successive bits of said PN bit sequence from said generator, d. means operative when said comparing means indicates the absence of identity between bits compared therein for conditioning said PN generator to generate said serial PN sequence as a function of said plurality of bits then stored in said storing means.

Claim 3

The invention as set forth in claim 1 further comprising means responsive to a plurality of bit comparisons by said comparing means indicative of the presence of identity between bits compared therein for indicating that the PN bit sequence generated by said PN sequence generator corresponds to said frame sync pattern.

Claim 4

The invention as set forth in claim 2 wherein said storing means comprises a plurality of registers each having storage for a successively larger number of bits of said input data and means for storing said successive pluralities of input data bits simultaneously in said register, means for parallel loading (a) the bits from those of said pluralities of registers having storage for smaller numbers of bits into those of said pluralities of registers having storage for a next larger number of bits, so long as said plurality of bit comparisons indicative of the presence of identify do not occur, and (b) the bits of the one of said registers having storage for the largest number of bits into said PN sequence generator.

Claim 5

The invention as set forth in claim 3 wherein said PN sequence generator includes a shift register having storage for a larger number of bits than said one of said registers, and each of said register is also a shift register, means for applying said input data serially to said PN sequence register and into each of said storage registers, and means for enabling the parallel loading between said registers so long as said plurality of bit comparisons indicative of the presence of identity do not occur.

Claim 6

The invention as set forth in claim 4 wherein said multiplexing system is adapted to multiplex data in accordance with a distributed format structure wherein said frame sync pattern is constituted of a like ordered bit in successive multi-bit serial words, and wherein said frame synchronizing system further comprises means for generating clock pulses at the rate of said bits of said frame sync pattern, and means responsive to the absence of a plurality of said bit comparisons indicative of the presence of identity for adjusting the rate of said clock pulses.

Claim 7

The invention as set forth in claim 5 including means responsive to said clock pulses for entering and shifting said input data bits in said PN sequence register and in said storage registers.

Claim 8

The invention as set forth in claim 6 wherein said means responsive to said pluraLity of successive comparisons by said comparing means comprises sequential testing means for registering a plurality of said comparisons indicative of the presence of identity upon occurrence of each of said clock pulses, and mode control means for indicating said plurality of presence of identity comparisons when a predetermined number is registered in said sequented testing means.

Claim 9

The invention as set forth in claim 7 wherein said comparing means is an exclusive OR gate having its inputs connected to receive bits from said input data which correspond to bits in said PN sequence generator register having a predetermined bit spacing less than the total number of bits in said frame sync pattern.

Claim 10

The invention as set forth in claim 8 wherein said bit spacing is three bits.

Claim 11

The invention as set forth in claim 1 wherein said input data is stored in an input register having storage for the bits in said frame sync pattern or an integral submultiple thereof, and wherein said storage means includes storage registers comprising a register for storing one bit and a plurality of additional succeeding registers each having storage for one bit in addition to the storage capacity of its preceding register, said PN sequence generator being a register and the one of said storage registers of highest bit storage capacity having the same number of stages as said PN sequence generator register, parallel loading inputs between like ordered stages of said storage registers and between said highest capacity storage register and said PN sequence register, parallel loading inputs to the one bit register and to the last stage of each of said storage registers respectively from the first stage of said input data register and from each succeeding stage of said input register, a first input to said exclusive OR gate being from the stage of said input register next succeeding the last stage which has an output to a parallel load input of the highest capacity one of said storage registers, and the second input to said exclusive OR gate being from the last stage of said PN sequence generator register.