US3798378A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frame synchronization system
Assignee: TDK Micronas GmbH
•
Filing: 1972-11-07
•
Granted: 1974-03-19
•
Expires: 1992-11-07
Abstract
Abstract There is disclosed herein a frame synchronization system for a binary data TDM signal including a multiframe having X superframes, each of the X superframes including M midframes, each of the M midframes including m subframes, and each of the m subframes including x ports or channel times. The data signal includes an overhead channel having overhead data including a first sync signal having a first predetermined pattern composed of Y bits disposed in adjacent ones of the M midframes and a second sync signal having a second predetermined pattern different than the first predetermined pattern composed of M bits, each of the M bits being disposed in a different one of the M midframes, where X, M, m, x and Y are all integers greater than one. The data bit rate clock is extracted from the data signal and applied to a cascade connection of a port counter, a subframe counter, a midframe counter and a superframe counter which together with decoding and gating logic associated with each of the above-mentioned counters produces local timing signals including a first reference signal for the first sync signal of the data signal and a second reference signal for the second sync signal of the data signal. In response to one of the local timing signals, such as the overhead channel port timing signal, the overhead data is demultiplexed from the data signal. A first comparator compares the first reference signal to the bits of the data signal to produce a first output signal indicating matches and mismatches between the first reference signal and the data bits. A second comparator circuit compares the overhead bits with the second reference signal and produces a second output signal indicative of the matches and mismatches therebetween. A decision circuit including a digital integrator in the form of an up-down counter and threshold detectors produce a first control signal when the output signal of the counter is equal to or less than a predetermined lower threshold level and a second control signal is produced when the output of the counter is equal to or greater than a predetermined upper threshold level. A mode control capable of producing signals indicative of three different modes of operation is coupled to the threshold detectors and responds to both of the control signals. Gates are coupled between the first and second comparators and the decision counter which under control of the mode control circuit output signal representing a first mode couples the first output signal to the decision counter and under control of the mode control circuit output signal representing a second mode couples the second output signal to the decision counter. The second reference signal is produced by the states of the stages of the superframe counter and in a third mode between the first and second modes mentioned hereinabove the overhead data, under control of the mode control circuit output signal representing the third mode, is coupled to the stages of the superframe counter to provide an assumed error free second reference signal. During the first mode of operation the first output signal is coupled to the decision counter and when the first control signal is below or equal to the lower threshold level and there is a mismatch indicated in the first output signal a gate disposed between the bit clock and the port counter is operated to block the application of the bit clock to the port counter to cause a shift in the phase of the local timing signals to establIsh and maintain synchronization to midframes of the received data signal. In the second mode of operation if the proper phase of the second sync signal is detected synchronization of the superframe and hence the multiframe is established and maintained. If the proper phase of the second sync signal is not detected, the mode control circuit will cause the framing circuit to revert to the first mode of operation and start the framing operation cycle again to properly establish and maintain the desired synchronization.
Inventors
- 👤 M Epstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:28
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/07; H04J3/073; H04J3/0602; H04J3/0605
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
370 words
A frame synchronization system for a time division multiplex binary data signal having a multiframe including X superframes, each of said X superframes including M midframes, each of said M midframes including m subframes, each of said m subframes including x ports, said data signal including an overhead data channel having at least a first sync signal having a first predetermined pattern composed of Y bits disposed in adjacent ones of said M midframes and a second sync signal having a second predetermined pattern different than said first predetermined pattern composed of M bits, each of said M bits being disposed in a different one of said M midframes, where x, M, m, x and Y are all integers greater than one, comprising: a source of said data signal; first means coupled to said source to produce timing signals including a first reference signal for said first sync signal and a second reference signal for said second sync signal; a first digital comparator coupled to said source and said first means responsive to said data signal and said first reference signal to produce a first output signal indicative of the matches and mismatches between said data signal and said first reference signal; a second digital comparator coupled to said source and said first means responsive to said data signal and said second reference signal to produce a second output signal indicative of the matches and mismatches between said second sync signal and said second reference signal; a second means responsive to said first output signal and said second output signal in sequence to produce a first control signal and a second control signal; third means coupled between said first and second comparators and the input of said second means and to the output of said second means responsive to said second control signal to control the coupling of said first and second output signals to the input of said second means; and fourth means coupled to said first means, said first comparator said second means and said third means responsive to said first output signal and said first control signals and under control of said third means to establish and maintain synchronization between said timing signals and said data signals.
Claim 2
Dependent Claim
370 words
A frame synchronization system for a time division multiplex binary data signal having a multiframe including X superframes, each of said X superframes including M midframes, each of said M midframes including m subframes, each of said m subframes including x ports, said data signal including an overhead data channel having at least a first sync signal having a first predetermined pattern composed of Y bits disposed in adjacent ones of said M midframes and a second sync signal having a second predetermined pattern different than said first predetermined pattern composed of M bits, each of said M bits being disposed in a different one of said M midframes, where x, M, m, x and Y are all integers greater than one, comprising: a source of said data signal; first means coupled to said source to produce timing signals including a first reference signal for said first sync signal and a second reference signal for said second sync signal; a first digital comparator coupled to said source and said first means responsive to said data signal and said first reference signal to produce a first output signal indicative of the matches and mismatches between said data signal and said first reference signal; a second digital comparator coupled to said source and said first means responsive to said data signal and said second reference signal to produce a second output signal indicative of the matches and mismatches between said second sync signal and said second reference signal; a second means responsive to said first output signal and said second output signal in sequence to produce a first control signal and a second control signal; third means coupled between said first and second comparators and the input of said second means and to the output of said second means responsive to said second control signal to control the coupling of said first and second output signals to the input of said second means; and fourth means coupled to said first means, said first comparator said second means and said third means responsive to said first output signal and said first control signals and under control of said third means to establish and maintain synchronization between said timing signals and said data signals.
Claim 3
Dependent Claim
37 words
A system according to claim 1, wherein each of said Y bits and each of said M bits are disposed in a given one of said x ports and in a different one of said m subframes.
Claim 4
Dependent Claim
30 words
A system according to claim 2, wherein Y is equal to two and said first pattern is alternate binary 0 and binary 1 in adjacent ones of said M midframes.
Claim 5
Dependent Claim
67 words
A system according to claim 3, wherein X is equal to 60, M is equal to 16 and m is equal to 4, each of said Y bits are present in the third of said m subframes in adjacent ones of said M midframes, and each of said m bits are present in the first of said m subframes of a different one of said M midframes.
Claim 6
Dependent Claim
44 words
A system according to claim 4, wherein the first two of said M bits of said second sync signal are a selected one of the binary bit sequences 10 and 01 and the remaining (M-2) bits of said second sync signal have any sequence.
Claim 7
Dependent Claim
51 words
A system according to claim 5, wherein said system is employed in an asynchronous demultiplexer, said data signal is rendered synchronous by employing a stuffing only technique, and a destuff command at said demultiplexer is conveyed by a predetermined number of bits of said M bits of said second sync signal.
Claim 8
Dependent Claim
47 words
A system according to claim 6, wherein said predetermined number of bits is the first two bits of said M bits of said second sync signal where the binary sequence 10 indicates the need of a destuffing action and the binary sequence 01 indicates no destuffing action.
Claim 9
Dependent Claim
65 words
A system according to claim 6, wherein said predetermined number of bits is the first 13 bits of said M bits of said second sync signal where the binary sequence 10 of the first two of the first 13 bits indicates the need of a destuffing action and the binary sequence 01 of the first two of the first 13 bits indicates no destuffing action.
Claim 10
Dependent Claim
89 words
A system according to claim 4, wherein said system is employed in an asynchronous demultiplexer, said data signal is rendered synchronous by employing a stuffing only technique, said M bits of said second sync signal have a first bit sequence of 01, AA, BB, CC, DD, EE, FF, GG to indicate a no destuffing action by said demultiplexer, and said M bits of said second sync signal have a second bit sequence of 10, AA, BB, CC, DD, EE, FF, GG to indicate a destuffing action by said demultiplexer.
Claim 11
Dependent Claim
37 words
A system according to claim 9, wherein the first 13 bits of said first bit sequence forms the no destuff control words, and the first 13 bits of said second bit sequence forms the destuff control word.
Claim 12
Dependent Claim
151 words
A system according to claim 1, wherein said first means includes fifth means coupled to said source to extract a bit rate clock from said data signal, a port counter coupled to said fifth means responsive to said bit rate clock, said port counter having a division factor equal to x, a subframe counter coupled to said port counter, said subframe counter having a division factor equal to m, a midframe counter coupled to said subframe counter, said midframe counter having a division factor equal to M, a superframe counter coupled to said midframe counter, said superframe counter having a division factor equal to X, first logic circuitry coupled to said port counter to produce said first reference signal, and the states of the stages of said superframe counter providing said second reference signal; and said first reference signal is the 1 output of the first stage of said midframe counter.
Claim 13
Dependent Claim
92 words
A system according to claim 11, further including sixth means coupled to said source and said logic circuitry responsive to said first reference signal to demultiplex said overhead channel data from said data signal, and seventh means coupled to said sixth means and said third means under control of said third means to clear said superframe counter and to load said overhead channel data into said superframe counter at a predetermined time between coupling said first output signal to said third means and coupling said second output signal to said third means.
Claim 14
Dependent Claim
80 words
A system according to claim 12, wherein said second means includes a decision counter, and a threshold detector having A first threshold level and a second threshold level higher than said first threshold level, said detector producing said first control signal when the signal from said decision circuit is equal to or less than said first threshold level and said second control signal when the signal from said decision circuit is equal to or greater than said second threshold level.
Claim 15
Dependent Claim
14 words
A system according to claim 13, wherein said decision counter includes an up-down counter.
Claim 16
Dependent Claim
120 words
A system according to claim 13, wherein said third means includes second logic circuitry coupled to said threshold detector responsive to said second control signal to produce third, fourth and fifth control signals sequentially in the order named, a first gate circuit coupled between said first comparator and said decision circuit controlled by said third control signal to couple said first output signal to said decision circuit, and a second gate circuit coupled between said second comparator and said decision circuit controlled by said fifth control signal to couple said second output signal to said decision circuit, said fourth control signal being coupled to said seventh means to control the loading of said overhead channel data into said superframe counter.
Claim 17
Dependent Claim
107 words
A system according to claim 15, wherein said fourth means includes third logic circuitry coupled to said first comparator, said threshold detector and said second logic circuitry responsive to said first output signal, said first control signal and said third control signal to produce a HALT signal during said third control signal when both said first output signal and said first control signal indicate an out-of-sync condition, and a third gate circuit coupled between said fifth means and said port counter to inhibit coupling said bit rate clock to said port counter to cooperate in establish and maintain synchronization between said timing signals and said data signals.
Claim 18
Dependent Claim
18 words
A system according to claim 16, wherein each of said first and second comparators is an EXCLUSIVE-NOR gate.
Claim 19
Dependent Claim
80 words
A system according to claim 1, wherein said second means includes a decision counter, and a threshold detector having a first threshold level and a second threshold level higher than said first threshold level, said detector producing said first control signal when the signal from said decision circuit is equal to or less than said first threshold level and said second control signal when the signal from said decision circuit is equal to or greater than said second threshold level.
Claim 20
Dependent Claim
14 words
A system according to claim 18, wherein said decision counter includes an up-down counter.
Claim 21
Dependent Claim
95 words
A system according to claim 1, wherein said third means includes logic circuitry coupled to said second means responsive to said second control signal to produce third and fourth control signals sequentially in the order named, a first gate circuit coupled between said first comparator and said second means controlled by said third control signal to couple said first output signal to said second means, and a second gate circuit coupled between said second comparator and said second means controlled by said fourth control signal to couple said second output signal to said second means.
Claim 22
Dependent Claim
63 words
A system according to claim 1, wherein said fourth means includes logic circuitry coupled to said first means, said first comparator, said second means and said third means, said logic circuitry being responsive to said first output signal and said first control signal and under control of said third means to establish and maintain synchronization between said timing signals and said data signals.
Claim 23
Dependent Claim
398 words
A frame synchronization system for a time division multiplex binary data signal having a multiframe including X superframes, each of said X superframes including M midframes, each of said M midframes including m subframes, each of said m subframes including x ports, said data signal including an overhead data channel having a first sync signal having a first predetermined pattern composed of Y bits disposed in adjacent ones of said M midframes and one of a second sync signal and a third sync signal, said second sync signal having a second predetermined pattern different than said first predetermined pattern composed of M bits, each of said M bits being disposed in a different one of said M midframes, and said third sync signal being the complement of said second sync signal, where X, M, m, x and Y are all integers greater than one, comprising: a source of said data signal; first means coupled to said source to produce timing signals including a first reference signal for said first sync signal and a second reference signal for said second and third sync signals; a first digital comparator coupled to said source and said first means responsive to said data signal and said first reference signal to produce a first output signal indicative of the matches and mismatches between said data signal and said first reference signal; a second digital comparator coupled to said source and said first means responsive to said data signal and said second reference signal to produce a second output signal indicative of the matches and mismatches between one of said second and third sync signals and said second reference signal; a second means responsive to said first output signal and said secpmd output signal in sequence to produce a first control signal and a second control signal; third means coupled between said first and second comparators and the input of said second means and to the output of said second means responsive to said second control signal to control the coupling of said first and second output signals to the input in said second means; and fourth means coupled to said first means, said first comparator, said second means and said third means responsive to said first output signal and said first control signal and under control of said third means to establish and maintain synchronization between said timing signals and said data signals.
Claim 24
Dependent Claim
398 words
A frame synchronization system for a time division multiplex binary data signal having a multiframe including X superframes, each of said X superframes including M midframes, each of said M midframes including m subframes, each of said m subframes including x ports, said data signal including an overhead data channel having a first sync signal having a first predetermined pattern composed of Y bits disposed in adjacent ones of said M midframes and one of a second sync signal and a third sync signal, said second sync signal having a second predetermined pattern different than said first predetermined pattern composed of M bits, each of said M bits being disposed in a different one of said M midframes, and said third sync signal being the complement of said second sync signal, where X, M, m, x and Y are all integers greater than one, comprising: a source of said data signal; first means coupled to said source to produce timing signals including a first reference signal for said first sync signal and a second reference signal for said second and third sync signals; a first digital comparator coupled to said source and said first means responsive to said data signal and said first reference signal to produce a first output signal indicative of the matches and mismatches between said data signal and said first reference signal; a second digital comparator coupled to said source and said first means responsive to said data signal and said second reference signal to produce a second output signal indicative of the matches and mismatches between one of said second and third sync signals and said second reference signal; a second means responsive to said first output signal and said secpmd output signal in sequence to produce a first control signal and a second control signal; third means coupled between said first and second comparators and the input of said second means and to the output of said second means responsive to said second control signal to control the coupling of said first and second output signals to the input in said second means; and fourth means coupled to said first means, said first comparator, said second means and said third means responsive to said first output signal and said first control signal and under control of said third means to establish and maintain synchronization between said timing signals and said data signals.
Claim 25
Dependent Claim
89 words
A system according to claim 22, wherein said system is employed in an asynchronous demultiplexer, said data signal is rendered synchronous by employing a stuffing only technique, said M bits of said second sync signal having a first bit sequence of 01, AA, BB, CC, DD, EE, FF, GG to indicate a no destuffing action by said demultiplexer, and said M bits of said third sync signal having a second said sequence of 10, AA, BB, CC, DD, EE, FF, GG to indicate a destuffing action by said demultiplexer.
Claim 26
Dependent Claim
37 words
A system according to claim 23, wherein the first 13 bits of said first bit sequence forms the no destuff control word, and the first 13 bits of said second bit sequence forms the destuff control word.
References Cited (Backward Citations)
US3662114A
Cited
US3754102A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-18 | 1977-09-17 | 1978-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-18 | 1981-09-17 | 1982-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-18 | 1985-09-17 | 1986-03-19 | $7700.00 | Window Closed / Lapsed |