Frame synchronization system

Abstract

Abstract Frame synchronization for a binary data signal including a superframe having M midframes, each of the M midframes, including m subframes is accomplished by providing within the data signal a first sync signal having a first predetermined pattern disposed in each of the M midframes and a second sync signal having a second predetermined pattern different than the first pattern composed of M bits, each of the M bits being disposed in a different one of the M midframes, wherein M and m are integers greater than 1, such as M 64 and m 15. A data bit rate clock is extracted from the data signal and applied to a cascade connection of digital dividers to provide local timing, including subframe rate timing signals, midframe rate timing signals, superframe rate timing signals, and a locally generated first sync signal. A typical arrangement of a six stage shift register (where M is typically equal to 64) and feedback logic generates locally the second sync signal. A first digital comparator compares the locally generated first sync signal with the first sync signal contained in the data signal and the resulting matches and mismatches are integrated in a digital integrator, such as an up-down counter. When the count of the digital integrator is below a predetermined count threshold and a mismatch is present at a time defining when the first sync signal contained in the data signal should occur relative to the local timing, a HALT signal is produced which inhibits the flow of bit rate clock pulses to the first counter of the cascade connected counters (dividers) so as to control the phase of the timing signals with respect to the data signal to establish and maintain synchronization of the local timing to the midframes of the data signal. The received second sync signal and the locally generated second sync signal are compared a bit at a time in a digital comparator, which produce as the result of bit errors in the received second sync signal or as the result of incorrect phase of the locally generated second sync signal matches and mismatches which also are applied to the digital integrating updown counter. When the count of the digital integrator is less than a second count threshold different than the first threshold, switching logic connects the received second sync signal to the shift register to provide therein error free bits of a portion of the received second sync signal which through the cooperation of the feedback logic generates an error free locally generated second sync signal so that in cooperation with synchronization of the midframe, the superframe is synchronized.

Inventors

• 👤 J Clark

Bibliographic Details