Frame search control for digital transmission system

Claim 2

In a receiver for recovering digital information from an incoming serial bit stream containing information bits and framing bits, and including a bit clock synchronized with the bit rate of the bit stream and an error density detector, a frame search control which comprises; a framing clock having an output terminal and an inhibit input terminal, and providing at a framing interval a pulse at said output terminal; means for sequentially storing n bits from the incoming bit stream, having a first input terminal arranged to accept the digital information from said bit stream, a second input terminal and an output terminal; a timing arrangement providing at an output terminal a series of n clock pulses at the bit rate following a framing interval when an in-frame condition exists said output terminal being connected to the second input terminal of said storing means whereby bits stored during the preceeding frame are read out and new bits are written in during the present frame; a comparator having one input connected to the output of said storing means, having a second input connected to receive said bit stream, said comparator providing an error indication for each violation of the framing pattern, said error indication being applied to said error density detector so as to change the state of the output when an out-of-frame indication occurs, i.e., when the number of error indications at the framing interval exceeds a predetermined ratio; and means for limiting the number of pulses in said series of clock pulses, said limiting means having an input connected to the output of said timing arrangement and being responsive to the comparator output and the state of the error density detector so as to provide a count of n when an in-frame condition exists and to increase the count by up to a predetermined number greater than n when both an error indication and an out-of-frame indication occur.

Claim 3

A frame search control in accordance with claim 1 wherein said means for limiting further comprises: counting means for counting the number of clock pulses, having a clock input connected to the output of said timing arrangement having programmed inputs under control of a load function terminal providing a first control signal at a first output, said first control signal having one binary state for clock pulse counts less than the n and the other binary state otherwise, and a second control signal at a second output, said second control signal having said one binary state for clock pulse counts less than a full count and the other binary state when a full count of 2n is reached; a first logic means having one input connected to the first output of said counting means, having a second input connected to the second output of said counting means, said first logic means providing at an output a binary value of one state when the first and second control signals are of the same state and of the other binary state otherwise; and second logic means having a first input connected to the output of said first logic means, having a second input connected to the output of said comparator and having a third input connected to the output of said error density detector, and having an output, said second logic means providing a load enable signal to the load function terminal of said counting means except when an error indication and an out-of-frame indication concur or the first and second control signals are in opposite states so that under an in-frame condition said counting means will cause said second control signal to change state when a count of n has been attained, and under an out-of-frame condition the load function input will be inhibited causing said counting means to count from a 0 count until either a correct comparison is made, thereby changing the state of the comparator output, or a count of 2n is obtained so as to permit a series of n additional clock pulses to occur and thus read into said storing means the next n bits from said bit stream.

Claim 4

A frame search control in accordance with claim 2 wherein said counting means further comprises: an m stage counter where 2 m-1 =n, having a count of m/2 (binary 100---0) connected to the programmed inputs to be read in immediately following the framing interval if the load function input is enabled, otherwise the count starts at zero, said first control signal is obtained from the output of the last counter stage, i.e., the most significant bit (MSB), and said second control signal is obtained from the carry output.

Claim 5

A frame search control in accordance with claim 3 wherein said first logic means further comprises: an inverter having the input connected to the carry output of said m stage counter, and providing the opposite binary states at an output; and an Exclusive-OR gate having a first input connected to the output of the last stage of said counter, having a second input connected to the output of said inverter and having an output.

Claim 6

A frame search control in accordance with claims 3 or 4 wherein said second logic means further comprises: a first AND-gate having a first input connected to the output of said first logic means, having a second input connected to the output of said error density detector, and having an output; a second AND-gate having a first input connected to the output of said first logic means, having a second input connected to the output of said comparator, and having an output; and a NOR-gate having inputs connected to the outputs of said first and second AND-gates and having an output connected to the load function input of said counter.

Claim 7

A frame search control in accordance with claim 1, 2 or 5 wherein said timing arrangement further comprises: an edge triggered flip-flop having a clock input connected to the pulse output of said framing clock, having a fixed binary state applied to the input, having a clear input and providing at the Q output an enable state on the occurrence of the framing clock pulse, and retaining the enable state output until a pulse appears at said clear input; a NOR-gate having a first input connected to the Q output of said flip-flop, having a second input connected to receive said bit clock pulses, and providing at an output the series of bit clock pulses while said flip-flop is in the enable state; and a NAND-gate having a first input connected to receive the bit clock pulses, having a second input connected to the carry output of said counter, and having an output connected to the clear input of said flip-flop, whereby a clear pulse is applied to said clear input to put the flip-flop in the disable state when the counter reaches a full count.