US4375102A
Expired / Lapsed
US
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Digital code word detection
Assignee: US Philips Corp
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Filing: 1980-07-29
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Granted: 1983-02-22
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Expires: 2000-07-29
Abstract
Abstract A method by which code words in a digital bit stream can be detected in a reliable manner without word synchronization, in an environment where the bit error rate is high. The bit stream is divided into data blocks having a number of bits equal to the number of bits of the code word. The number of times that the same bit state is detected in a plurality of blocks in the same relative position in the data block is accumulated. For each bit position the accumulated value is compared with a threshold value and when the threshold value for each bit position is exceeded, the code word is detected from the digital state of the accumulated value. The cyclic permutation of the bits of the code word and the code word itself represent one and the same message. In a device using this method, a bit counter feeds a word counter with the bit stream applied at an output, a shift register receiving each data block as effectively formed by the word counter. Counters count the "1" and "0" occurrences in each shift register section in successive data blocks. Threshold devices provide outputs when their thresholds as given by generators and are exceeded. The outputs are gated by combinatorial logic gates, to record a detected code word in a register 33 which addresses a store 33 to find the associated message.
Inventors
- 👤 Andreas J. W. Van Daal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:16
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/12; H04L1/16; H04L1/18; H04J; H04J3/00; H04J3/02; H04J3/12; H04L1/08; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/39
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
161 words
A method of detecting a message in the form of a digital code word, the digital code word containing a sequence of a predetermined number of bits and being included a few times consecutively and sequentially in a bit stream, characterized in that the bit stream is randomly divided into data blocks, each data block having a number of bits which is equal to the number of bits of the digital code word; the digital bit state is determined and recorded for each bit position in the data block; the recorded data of each bit position are accumulated for a plurality of consecutive data blocks; the accumulated value of the recorded data of each bit position for a plurality of data blocks is compared with a threshold value; the digital code word is detected from the digital state of the accumulated values when the threshold value for each bit position in a plurality of data blocks has at least been reached.
Claim 2
Independent Claim
161 words
A method of detecting a message in the form of a digital code word, the digital code word containing a sequence of a predetermined number of bits and being included a few times consecutively and sequentially in a bit stream, characterized in that the bit stream is randomly divided into data blocks, each data block having a number of bits which is equal to the number of bits of the digital code word; the digital bit state is determined and recorded for each bit position in the data block; the recorded data of each bit position are accumulated for a plurality of consecutive data blocks; the accumulated value of the recorded data of each bit position for a plurality of data blocks is compared with a threshold value; the digital code word is detected from the digital state of the accumulated values when the threshold value for each bit position in a plurality of data blocks has at least been reached.
Claim 3
Dependent Claim
27 words
A method of detecting a digital code word as claimed in claim 1, characterized in that the digital code word and the bit stream contain binary data.
Claim 4
Dependent Claim
64 words
A method of detecting a digital code word as claimed in claim 2, characterized in that the number of times a first digital state of each bit of the data block is determined is accumulated by a first accumulator and that the number of times a second digital state of each bit of the data block is determined is accumulated by a second accumulator.
Claim 5
Dependent Claim
52 words
A method of detecting a digital code word as claimed in claim 2, characterized in that a first digital state of each bit of the data block is accumulated with a positive sign and that a second digital state of each bit of the data block is accumulated with a negative sign.
Claim 6
Dependent Claim
60 words
A method of detecting a digital code word as claimed in claim 4, characterized in that: a data block is compared with a preceding data block; the number of times data blocks are consecutively and sequentially identical is accumulated; and when a threshold value is reached by the accumulated value, the digital code word is identical to the data block.
Claim 7
Dependent Claim
188 words
A code detector for detecting a message in the form of a digital code word, the digital code word containing a sequence of a predetermined number of bits and being included at least two times consecutively and sequentially in a bit stream comprising: a shift register having a number of sections equal to the number of bits (N) of the digital code word, each section having an output, means for randomly dividing the bit stream into data blocks of N bits, these data blocks being applied to an input of the shift register, the output of each section being coupled to associated counting means for determining the number of times that the same digital state of the bit has occurred in each section in a plurality of data blocks, and the code detector further comprising threshold devices each having a first input for receiving a threshold value and a second input connected to the asociated counting means, and an output, the outputs of the threshold devices providing signal values, which are a representation of the digital code word, when the threshold value of each threshold device is exceeded.
Claim 8
Dependent Claim
188 words
A code detector for detecting a message in the form of a digital code word, the digital code word containing a sequence of a predetermined number of bits and being included at least two times consecutively and sequentially in a bit stream comprising: a shift register having a number of sections equal to the number of bits (N) of the digital code word, each section having an output, means for randomly dividing the bit stream into data blocks of N bits, these data blocks being applied to an input of the shift register, the output of each section being coupled to associated counting means for determining the number of times that the same digital state of the bit has occurred in each section in a plurality of data blocks, and the code detector further comprising threshold devices each having a first input for receiving a threshold value and a second input connected to the asociated counting means, and an output, the outputs of the threshold devices providing signal values, which are a representation of the digital code word, when the threshold value of each threshold device is exceeded.
Claim 9
Dependent Claim
103 words
A code detector as claimed in claim 6 characterized in that the counting means comprise a first and a second group of N counters, one counter of each group being coupled to one of the sections of the shift register, the first group of counters accumulating the number of times the first digital state of the bits of the data block in a preceding number of data blocks has been determined, and the second group of counters accumulating the number of times the other digital state of the bits of the data block in the preceding number of data blocks has been determined.
Claim 10
Dependent Claim
71 words
A code detector as claimed in claim 6 characterized in that the counting means comprise a group of N counters, each section of the shift register being coupled to the associated counter, the count of the counters being increased by one unit when the first digital state of the data block has been determined and reduced by one unit when the second digital state of the data block has been determined.
Claim 11
Dependent Claim
91 words
A code detector as claimed in claim 8, characterized in that the code detector comprises a further shift register having N sections each having an output, that the corresponding outputs of the two shift registers are connected to exclusive OR-gate circuits to determine bit agreement in the corresponding sections, that outputs of the N exclusive OR-gate circuits are connected to inputs of a NAND-gate circuit, and that an output of the NAND-gate circuit is connected to a counting element for accumulating the number of times consecutively sequential data blocks are identical.
References Cited (Backward Citations)
US3463911A
Cited
US4271520A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-21 | 1986-08-23 | 1987-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-21 | 1990-08-23 | 1991-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-21 | 1994-08-23 | 1995-02-22 | $7700.00 | Window Closed / Lapsed |