US3842399A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Repetitive byte recognition circuit
Assignee: AT&T Inc
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Filing: 1974-01-02
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Granted: 1974-10-15
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Expires: 1994-01-02
Abstract
Abstract Data bytes, encoded into successive groups of n repetitive data bytes, are recovered by selecting a first data byte in each of the successive groups. The first data byte is identified by detecting mismatches in the corresponding bits of successive data bytes. A data byte selector which selects every nth byte is aligned in time with the identification of this first data byte and the first data byte of each successive group is selected. In the presence of transmission errors there occurs more than one mismatched data byte within the span of n data bytes. In this event the identified data byte is ignored and the selection of a data byte is accomplished independent of the alignment in time between the data byte selector and the identified data byte.
Inventors
- 👤 J Kneuer
- 👤 W Lawless
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 02:04
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/08; H04L25/00; H04L25/02; H04L25/05
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
57 words
A circuit for recovering multibit data bytes encoded into successive groups of n repetitive data bytes, comprising, means for selecting every nth one of the encoded data bytes; means for detecting mismatches in corresponding bits of successive encoded data bytes; and means repsonsive to the mismatch detection for aligning, in time, the operation of the selecting means.
Claim 2
Dependent Claim
57 words
A circuit for recovering multibit data bytes encoded into successive groups of n repetitive data bytes, comprising, means for selecting every nth one of the encoded data bytes; means for detecting mismatches in corresponding bits of successive encoded data bytes; and means repsonsive to the mismatch detection for aligning, in time, the operation of the selecting means.
Claim 3
Dependent Claim
64 words
A circuit in accordance with claim 1 wherein the aligning means includes error count means responsive to the mismatch detection by the detecting means for indicating a second mismatched data byte within the span of an n byte count; and means responsive to the indication of the second mismatched data byte for rendering the operation of the selecting means independent of the aligning means.
Claim 4
Dependent Claim
49 words
A circuit in accordance with claim 2 wherein the error count means includes n byte count means responsive to the mismatch detection for initiating an n byte count interval and means responsive to a mismatch detection during the n byte count interval for indicating the second mismatched data byte.
Claim 5
Dependent Claim
36 words
A circuit in accordance with claim 1 wherein the selecting means includes means for counting n encoded data bytes and means for enabling data byte selection in response to a predetermined state of the counting means.
Claim 6
Dependent Claim
26 words
A circuit in accordance with claim 4 wherein the aligning means further includes means for identifying the nth data byte subsequent to the mismatched data byte.
Claim 7
Dependent Claim
51 words
A circuit in accordance with claim 5 wherein there is further included means for placing the counting means into the predetermined state in response to the identification of the nth data byte subsequent to the mismatched data byte, whereby data byte selection is aligned in time with the identified data byte.
Claim 8
Dependent Claim
35 words
A circuit in accordance with claim 6 wherein the aligning means includes second count means for counting n data bytes and means responsive to the detection of a mismatch for enabling said second count means.
Claim 9
Dependent Claim
83 words
A circuit for aligning in time the counting cycle of an n count binary counter with a predetermined data byte in each of a plurality of successive groups of n repetitive data bytes, the circuit comprising, means for detecting mismatches in the corresponding bits of successive data bytes; means responsive to the detecting means for identifying the nth data byte subsequent to the mismatched data byte; and means responsive to the identifying means for setting the binary counter to a predetermined count state.
Claim 10
Dependent Claim
83 words
A circuit for aligning in time the counting cycle of an n count binary counter with a predetermined data byte in each of a plurality of successive groups of n repetitive data bytes, the circuit comprising, means for detecting mismatches in the corresponding bits of successive data bytes; means responsive to the detecting means for identifying the nth data byte subsequent to the mismatched data byte; and means responsive to the identifying means for setting the binary counter to a predetermined count state.
Claim 11
Dependent Claim
36 words
A circuit in accordance with claim 8 wherein the identifying means includes means for counting n data bytes subsequent to the mismatched data byte and means enabled by the detected mismatch for enabling the counting means.
Claim 12
Dependent Claim
33 words
A circuit in accordance with claim 9 wherein there is further included means responsive to the predetermined count state of the binary counter for recovering the predetermined data byte aligned in time therewith.
References Cited (Backward Citations)
US3772649A
Cited
US3798549A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-14 | 1978-04-15 | 1978-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-14 | 1982-04-15 | 1982-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-14 | 1986-04-15 | 1986-10-15 | $7700.00 | Window Closed / Lapsed |