Logic circuit having voltage booster

Claim 2

A logic circuit comprising: voltage boosting means connected to a power source voltage, said voltage boosting means receiving an input signal and having an output for supplying an output signal, said voltage boosting means being constructed and arranged so that the voltage level of said output signal is boosted above the level of said power source voltage when said input signal changes to a predetermined level; voltage retaining means having an output end for outputting an auxiliary voltage higher than said power source voltage; and switching means connected between said output end of said voltage retaining means and said voltage boosting means and being responsive to said boosting operation of said voltage boosting means to connect said auxiliary voltage to said output of said voltage boosting means.

Claim 3

A circuit according to claim 1, wherein said switching means comprises a depletion-type MOS transistor connected between said output of said voltage boosting means and said output end of said voltage retaining means and means for keeping said depletion-type MOS transistor in cut-off state before the level of said input signal is changed to said predetermined level.

Claim 4

A circuit according to claim 1, wherein said switching means comprises an enhancement-type MOS transistor connected between said output of said voltage boosting means and said output end of said voltage retaining means and booster means connected to the gate of said enhancement-type MOS transistor.

Claim 5

A circuit according to claim 1, wherein said switching means comprises first, second and third depletion-type MOS transistors and a first end, said first depletion-type MOS transistor being inserted between said output end of said voltage retaining means and said first end, said second depletion-type MOS transistor being inserted between said power source voltage and said first end, said third depletion-type MOS transistor being inserted between said first end and said output of said voltage boosting means, a gate of said second depletion-type MOS transistor receiving a signal which causes said second depletion-type MOS transistor to turn off when the voltage of said input signal is boosted by said voltage boosting means, and gates of said first and third depletion-type MOS transistors receiving a signal which causes said first and third depletion-type MOS transistors to simultaneously turn on when the voltage level of said output signal is boosted by said voltage boosting means.

Claim 6

A circuit according to claim 4, wherein said second depletion-type MOS transistor has a transconductance gm which is sufficiently greater than the transconductance gm of said third depletion-type MOS transistor.

Claim 7

A circuit according to claim 1, wherein said switching means comprises first and second enhancement-type MOS transistors, an oscillator, a capacitor and a first end, said first enhancement-type MOS transistor being inserted between said output end of said voltage retaining means and said output of said voltage boosting means, said second enhancement-type MOS transistor being inserted between said signal input end and said first end connected to a gate of said first enhancement-type MOS transistor, the gate of said second enhancement-type MOS transistor being supplied with a predetermined bias, and said capacitor being inserted between an output of said oscillator and said first end.

Claim 8

A circuit according to claim 1, wherein said switching means comprises first, second, third and fourth enhancement-type MOS transistors, an oscillator, a capacitor and first, second and third ends, said first enhancement-type MOS transistor being inserted between said output end of said voltage retaining means and said output to said voltage boosting means, said capacitor having one end which is connected to an output end of said oscillator and the other end which is connected to said first end, and second enhancement-type MOS transistor being inserted between said first end and said second end connected to a gate of said first enhancement-type MOS transistor, the gate of said second enhancement-type MOS transistor being connected to said first end, the gate of said third enhancement-type MOS transistor being supplied with a predetermined bias, said third enhancement-type MOS transistor being inserted between said first end and said third end at which a voltage corresponding to said input signal is obtained, and said fourth enhancement-type MOS transistor being inserted between said second end and said third end and the gate of said fourth enhancement-type MOS transistor being supplied with a predetermined bias.

Claim 9

A logic circuit comprising: a plurality of voltage boosting means connected to a power source voltage, said plurality of voltage boosting means receiving a plurality of input signals and having a plurality of outputs for supplying a plurality of output signals, said plurality of voltage boosting means being constructed and arranged so that the voltage levels of said plurality of output signals are boosted above the level of said power source voltage when said plurality of input signals change to a predetermined level; voltage retaining means having an output end for outputting an auxiliary voltage higher than said power source voltage; and a plurality of switching means connected between said output end of said voltage retaining means and said plurality of voltage boosting means, each being responsive to said boosting operation of one of said plurality of voltage boosting means to connect said auxiliary voltage to one of said plurality of outputs of said plurality of voltage boosting means.

Claim 10

A logic circuit comprising: a plurality of voltage boosting means connected to a power source voltage, said plurality of voltage boosting means receiving a plurality of input signals and having a plurality of outputs for supplying a plurality of output signals, said plurality of voltage boosting means being constructed and arranged so that the voltage levels of said plurality of output signals are boosted above the level of said power source voltage when said plurality of input signals change to a predetermined level; voltage retaining means having an output end for outputting an auxiliary voltage higher than said power source voltage; and a plurality of switching means connected between said output end of said voltage retaining means and said plurality of voltage boosting means, each being responsive to said boosting operation of one of said plurality of voltage boosting means to connect said auxiliary voltage to one of said plurality of outputs of said plurality of voltage boosting means.

Claim 11

A circuit according to claim 8, wherein each of said plurality of switching means comprises first, second and third depletion-type MOS transistors and a first end, said first depletion-type MOS transistor being inserted between said output end of said voltage retaining means and said first end, said second depletion-type MOS transistor being inserted between said power source voltage and said first end, said third depletion-type MOS transistor being inserted between said first end and one of said plurality of outputs of said plurality of voltage boosting means, a gate of said second depletion-type MOS transistor receiving a signal which causes said second depletion-type MOS transistor to turn off when the voltage of one of said plurality of input signals is boosted by said voltage boosting means, and gates of said first and third depletion-type MOS transistors receiving a signal which causes said first and third depletion-type MOS transistors to simultaneously turn on when the voltage of said output signal is boosted by said voltage boosting means.

Claim 12

A circuit according to claim 9, wherein said second depletion-type MOS transistor has a transconductance gm which is sufficiently greater than a transconductance gm of said third depletion-type MOS transistor.

Claim 13

A circuit according to claim 8, wherein each of said switching means comprises first and second enhancement-type MOS transistors, an oscillator, a capacitor and a first end, said first enhancement-type MOS transistor being inserted between said output end of said voltage retaining means and one of said plurality of output ends of said plurality of voltage boosting means, said second enhancement-type MOS transistor being inserted between one of said plurality of input signals and said first end connected to a gate of said first enhancement-type MOS transistor, the gate of said second enhancement-type MOS transistor being supplied with a predetermined bias, and said capacitor being inserted between an output end of said oscillator and said first end.

Claim 14

A circuit according to claim 8, wherein each of said switching means comprises first, second, third and fourth enhancement-type MOS transistors, an oscillator, a capacitor and first, second and third ends, said first enhancement-type MOS transistor being inserted between said output end of said voltage retaining means and one of said plurality of outputs of said plurality of voltage boosting means, said capacitor having one end which is connected to an output end of said oscillator and the other end which is connected to said first end, said second enhancement-type MOS transistor being inserted between said first end and said second end connected to a gate of said first enhancement-type MOS transistor, the gate of said second enhancement-type MOS transistor being connected to said first end, said third enhancement-type MOS transistor being inserted between said first end and said third end at which a voltage corresonding to said input signal is obtained, the gate of said third enhancement-type MOS transistor being supplied with a predetermined bias, and said fourth enhancement-type MOS transistor being inserted between said second end and said third end, the gate of said fourth enhancement-type MOS transistor being supplied with a predetermined bias.

Claim 15

A logic circuit comprising: voltage boosting means connected to a power source voltage, said voltage boosting means receiving an input signal and having an output for supplying an output signal and having an internal boosted voltage end for obtaining an internal boosted voltage, said voltage boosting means being constructed and arranged so that the voltage level of said internal boosted voltage is boosted above the level of said power source voltage when said input signal changes to a predetermined level and so that the voltage level of said output signal is boosted above the level of said power source voltage when said internal boosted voltage is boosted; voltage retaining means having an output end for outputting an auxiliary voltage higher than said power source voltage; and switching means connected between said output end of said voltage retaining means and said voltage boosting means and being responsive to said boosting operation of said voltage boosting means to connect said auxiliary voltage to said output of said voltage boosting means.

Claim 16

A logic circuit comprising: voltage boosting means connected to a power source voltage, said voltage boosting means receiving an input signal and having an output for supplying an output signal and having an internal boosted voltage end for obtaining an internal boosted voltage, said voltage boosting means being constructed and arranged so that the voltage level of said internal boosted voltage is boosted above the level of said power source voltage when said input signal changes to a predetermined level and so that the voltage level of said output signal is boosted above the level of said power source voltage when said internal boosted voltage is boosted; voltage retaining means having an output end for outputting an auxiliary voltage higher than said power source voltage; and switching means connected between said output end of said voltage retaining means and said voltage boosting means and being responsive to said boosting operation of said voltage boosting means to connect said auxiliary voltage to said output of said voltage boosting means.

Claim 17

A circuit according to claim 13, wherein said voltage retaining means has a first output end and a second output end to respectively steadily produce first and second auxiliary voltages higher than said power source voltage and said switching means comprises first, second and third depletion-type MOS transistors and a first end, said first depletion-type MOS transistor being inserted between said first output end of said voltage retaining means and said first end, said second depletion-type MOS transistor being inserted between said power source voltage and said first end, said third depletion-type MOS transistor being inserted between said first end and said internal boosted voltage end, a gate of said second depletion-type MOS transistor receiving a signal which causes said second depletion-type MOS transistor to turn off when the voltage level of said output signal is boosted by said voltage boosting means, and gates of said first and third depletion-type MOS transistors receiving a signal which causes said first and third depletion-type MOS transistors to simultaneously turn on when the voltage level of said output signal is boosted by said voltage boosting means.

Claim 18

A circuit according to claim 14, wherein said second depletion-type MOS transistor has a transconductance gm which is sufficiently greater than a transconductance gm of said third depletion-type MOS transistor.

Claim 19

A circuit according to claim 13, wherein said voltage retaining means has a first output end and a second output end to respectively steadily produce first and second auxiliary voltages higher than said power source voltage and said voltage boosting means comprises first, second and third MOS transistors, an inverter and a capacitor, said first MOS transistor being inserted between said second output end of said voltage retaining means and said output end of said voltage boosting means, a gate of said first MOS transistor being connected to said internal boosted voltage end, said inverter being connected to invert said input signal, said second MOS transistor being inserted between said output of said voltage boosting means and ground, a gate of said second MOS transistor being connected to an output end of said inverter, said third MOS transistor being inserted between said input signal and said internal boosted voltage end, the gate of said third MOS transistor being connected to said output end of said inverter, and said capacitor being connected between the gate of said first MOS transistor and said outputs of said voltage boosting means.

Claim 20

A circuit according to claim 16, wherein said first and second MOS transistors are of an enhancement type.

Claim 21

A logic circuit comprising: voltage boosting means connected to a power source voltage, said voltage boosting means receiving an input signal and having an output for supplying an output signal and having an internal boosted voltage end for obtaining an internal boosted voltage, said voltage boosting means being constructed and arranged so that the voltage level of said internal boosted voltage is boosted above the level of said power source voltage when said input signal changes to a predetermined level and so that the voltage level of said output signal is boosted above the level of said power source voltage when said internal boosted voltage is boosted; voltage retaining means having an output end, coupled to the output of said voltage boosting means, for outputting an auxiliary voltage higher than said power source voltage; and voltage generating means for producing said internal boosted voltage higher than said power source voltage at said internal boosted voltage end.

Claim 22

A logic circuit comprising: voltage boosting means connected to a power source voltage, said voltage boosting means receiving an input signal and having an output for supplying an output signal and having an internal boosted voltage end for obtaining an internal boosted voltage, said voltage boosting means being constructed and arranged so that the voltage level of said internal boosted voltage is boosted above the level of said power source voltage when said input signal changes to a predetermined level and so that the voltage level of said output signal is boosted above the level of said power source voltage when said internal boosted voltage is boosted; voltage retaining means having an output end, coupled to the output of said voltage boosting means, for outputting an auxiliary voltage higher than said power source voltage; and voltage generating means for producing said internal boosted voltage higher than said power source voltage at said internal boosted voltage end.

Claim 23

A circuit according to claim 18, wherein said voltage boosting means comprises first, second and third MOS transistors, an inverter and a capacitor, said first MOS transistor being inserted between said output end of said voltage retaining means and said output of said voltage boosting means, a gate of said first MOS transistor being connected to said internal boosted voltage end, said inverter being connected to invert said input signal, said second MOS transistor being inserted between said output of said voltage boosting means and ground, a gate of said second MOS transistor being connected to an output end of said inverter, said third MOS transistor being inserted between said input signal and said internal boosted voltage end, the gate of said third MOS transistor being supplied with a predetermined bias, and said capacitor being connected between the gate of said first MOS transistor and said output of said voltage boosting means.

Claim 24

A circuit according to claim 19, wherein said first and second MOS transistors are of an enhancement type.

Claim 25

A logic circuit comprising: a plurality of voltage boosting means connected to a power source voltage, said plurality of voltage boosting means receiving a plurality of input signals and having a plurality of outputs for supplying a plurality of output signals and having a plurality of internal boosted voltage ends for obtaining a plurality of internal boosted voltages, said plurality of voltage boosting means being constructed and arranged so that the voltage levels of said plurality of internal boosted voltages are boosted above the level of said power source voltage when said plurality of input signals change to a predetermined level and so that the voltage levels of said plurality of output signals are boosted above the level of said power source voltage when said plurality of internal voltages are boosted; voltage retaining means having an output end for outputting an auxiliary voltage higher than said power source voltage; and a plurality of switching means respectively arranged between said output end of said voltage retaining means and said plurality of internal boosted voltage ends, each being responsive to said boosting operation of one of said plurality of voltage boosting means to connect said auxiliary voltage to one of said plurality of outputs of said plurality of voltage boosting means.

Claim 26

A logic circuit comprising: a plurality of voltage boosting means connected to a power source voltage, said plurality of voltage boosting means receiving a plurality of input signals and having a plurality of outputs for supplying a plurality of output signals and having a plurality of internal boosted voltage ends for obtaining a plurality of internal boosted voltages, said plurality of voltage boosting means being constructed and arranged so that the voltage levels of said plurality of internal boosted voltages are boosted above the level of said power source voltage when said plurality of input signals change to a predetermined level and so that the voltage levels of said plurality of output signals are boosted above the level of said power source voltage when said plurality of internal voltages are boosted; voltage retaining means having an output end for outputting an auxiliary voltage higher than said power source voltage; and a plurality of switching means respectively arranged between said output end of said voltage retaining means and said plurality of internal boosted voltage ends, each being responsive to said boosting operation of one of said plurality of voltage boosting means to connect said auxiliary voltage to one of said plurality of outputs of said plurality of voltage boosting means.