Circuit using insulated-gate field-effect transistors

Claim 2

A circuit comprising a first insulated-gate, field-effect transistor coupled at its drain to a power source, at its gate to a signal input terminal and at its source to a first circuit node, a second insulated-gate, field-effect transistor which is coupled at its drain to said power source and at its gate to said first node, an oscillator circuit means driven by the said power source, and a first capacitor coupled between said first node and the output of said oscillator circuit means, whereby an output signal having a potential level of said power source appears at the source of said second transistor in response to an input signal appearing at said input terminal.

Claim 3

The circuit according to claim 1, further comprising a delay circuit having an input terminal for receiving said input signal and a second capacitor coupled between the source of said first transistor and an output terminal of said delay circuit.

Claim 4

The circuit according to claim 2, wherein said input signal has a potential of said power source.

Claim 5

A circuit comprising a first insulated-gate, field-effect transistor having a drain supplied from a power source and a gate supplied with an input signal, a first capacitor means having a first electrode coupled to the source of said first transistor, a delay circuit means having an input electrode supplied with said input signal and an output electrode coupled to a second electrode of said first capacitor means, a second insulated-gate, field-effect transistor having a drain supplied with said power source and a gate coupled to a source of said first transistor, a second capacitor means having a first electrode coupled to said gate of said second transistor and an oscillator means having an output terminal coupled to a second electrode of said second capacitor means.

Claim 6

A circuit comprising a first insulated-gate, field-effect transistor having a drain supplied from a power source and a gate supplied with an input signal, a first capacitor means having a first electrode coupled to the source of said first transistor, a delay circuit means having an input electrode supplied with said input signal and an output electrode coupled to a second electrode of said first capacitor means, a second insulated-gate, field-effect transistor having a drain supplied with said power source and a gate coupled to a source of said first transistor, a second capacitor means having a first electrode coupled to said gate of said second transistor and an oscillator means having an output terminal coupled to a second electrode of said second capacitor means.

Claim 7

A circuit comprising a first insulated-gate, field-effect transistor which is coupled at its drain to a power source, at its gate to an input terminal and at its source to a first node, a second insulated-gate, field-effect transistor which is coupled at its drain to said power source and at its gate to the first node, a delay circuit means coupled to receive said input signal and to produce an output signal in phase with said input signal, a first capacitor coupled between said first node and an output terminal of said delay circuit mean, an oscillator circuit means driven by said power source, a second capacitor coupled between said first node and the output of said oscillator means, whereby an output signal maintained at a potential level of said power source is produced at the source of said second transistor in response to said input signal.

Claim 8

A circuit comprising a first insulated-gate, field-effect transistor which is coupled at its drain to a power source, at its gate to an input terminal and at its source to a first node, a second insulated-gate, field-effect transistor which is coupled at its drain to said power source and at its gate to the first node, a delay circuit means coupled to receive said input signal and to produce an output signal in phase with said input signal, a first capacitor coupled between said first node and an output terminal of said delay circuit mean, an oscillator circuit means driven by said power source, a second capacitor coupled between said first node and the output of said oscillator means, whereby an output signal maintained at a potential level of said power source is produced at the source of said second transistor in response to said input signal.

Claim 9

The circuit according to claim 1, 4 or 5, wherein said input signal is a clock signal and the frequency of the output signal of said oscillator circuit means is greater than that of said clock signal.

Claim 10

A circuit comprising a power terminal for receiving a power voltage, a bootstrap node, a first insulated-gate field-effect transistor, means for connecting a drain of said first insulated-gate field-effect transistor to said power terminal, means for connecting a gate of said insulated-gate field-effect transistor to said bootstrap node, a second insulated-gate field-effect transistor having a source coupled to said bootstrap node, a first capacitor coupled to said bootstrap node, control means responsive to input signals of a given frequency for controlling said first capacitor and said second insulated-gate field-effect transistor to generate a potential having a value which is larger than said power voltage as it appears at said bootstrap node, a second capacitor having a first terminal coupled to said bootstrap node, oscillator means for generating an oscillation signal, and means for supplying said oscillation signal to a second terminal, whereby output signals having the same value as said power voltage are derived from a source of said first insulated-gate field-effect transistor, substantially in response to said input signals.

Claim 11

A circuit comprising a power terminal for receiving a power voltage, a bootstrap node, a first insulated-gate field-effect transistor, means for connecting a drain of said first insulated-gate field-effect transistor to said power terminal, means for connecting a gate of said insulated-gate field-effect transistor to said bootstrap node, a second insulated-gate field-effect transistor having a source coupled to said bootstrap node, a first capacitor coupled to said bootstrap node, control means responsive to input signals of a given frequency for controlling said first capacitor and said second insulated-gate field-effect transistor to generate a potential having a value which is larger than said power voltage as it appears at said bootstrap node, a second capacitor having a first terminal coupled to said bootstrap node, oscillator means for generating an oscillation signal, and means for supplying said oscillation signal to a second terminal, whereby output signals having the same value as said power voltage are derived from a source of said first insulated-gate field-effect transistor, substantially in response to said input signals.

Claim 12

The circuit according to claim 7, in which said control means includes a delay circuit means for generating delay signals responsive to said input signals, and means for supplying said delay signals to a second terminal of said first capacitor.

Claim 13

The circuit according to claim 7, in which said oscillation signal has a frequency which is higher than the frequency of said input signals.

Claim 14

An output circuit comprising first to third nodes, a power supply terminal for receiving a power voltage; first bootstrap circuit means responsive to input signals for operatively raising a potential at said first node to a level which is higher than the level of said power voltage; second bootstrap circuit means responsive to said input signals for operatively raising a potential at said second node to a level which is higher than the level of said power voltage; third bootstrap circuit means responsive to said input signals for operatively raising a potential at said third node to a level which is higher than the level of said power voltage; an output terminal; a first insulated-gate field-effect transistor having a drain coupled to said power supply terminal, a gate coupled to said first node, and a source coupled to said output terminal; a second insulated-gate field-effect transistor having a drain coupled to said power supply terminal, a gate coupled to said second node, and a source coupled to said output terminal; a third insultated-gate field-effect transistor having a drain coupled to said power supply terminal, a gate coupled to said third node and a source coupled to said second node; a second capacitor having a first terminal coupled to said third node; first means for generating a first oscillation signal with a given phase; second means for generating a second oscillation signal having different phase from said given phase; third means for supplying a second terminal of said first capacitor with said first oscillation signal; and means for supplying a second terminal of said second capacitor with said second oscillation signal, whereby an output signal of said power voltage is derived from said output terminal, in response to said input signals.

Claim 15

An output circuit comprising first to third nodes, a power supply terminal for receiving a power voltage; first bootstrap circuit means responsive to input signals for operatively raising a potential at said first node to a level which is higher than the level of said power voltage; second bootstrap circuit means responsive to said input signals for operatively raising a potential at said second node to a level which is higher than the level of said power voltage; third bootstrap circuit means responsive to said input signals for operatively raising a potential at said third node to a level which is higher than the level of said power voltage; an output terminal; a first insulated-gate field-effect transistor having a drain coupled to said power supply terminal, a gate coupled to said first node, and a source coupled to said output terminal; a second insulated-gate field-effect transistor having a drain coupled to said power supply terminal, a gate coupled to said second node, and a source coupled to said output terminal; a third insultated-gate field-effect transistor having a drain coupled to said power supply terminal, a gate coupled to said third node and a source coupled to said second node; a second capacitor having a first terminal coupled to said third node; first means for generating a first oscillation signal with a given phase; second means for generating a second oscillation signal having different phase from said given phase; third means for supplying a second terminal of said first capacitor with said first oscillation signal; and means for supplying a second terminal of said second capacitor with said second oscillation signal, whereby an output signal of said power voltage is derived from said output terminal, in response to said input signals.

Claim 16

A circuit comprising a plurality of insulated-gate field-effect transistors, means for supplying drains of said plurality of insulated-gate field-effect transistors from a power source, a plurality of capacitors each having a first terminal coupled to a gate of an associated one of said field-effect transistors, a plurality of oscillating means for generating oscillation signals having different phases, means for supplying said oscillation signals to second terminals of said capacitors, an output terminal, and means for commonly connecting sources of said plurality of insulated-gate field-effect transistors to said output terminal.

Claim 17

A circuit comprising a plurality of insulated-gate field-effect transistors, means for supplying drains of said plurality of insulated-gate field-effect transistors from a power source, a plurality of capacitors each having a first terminal coupled to a gate of an associated one of said field-effect transistors, a plurality of oscillating means for generating oscillation signals having different phases, means for supplying said oscillation signals to second terminals of said capacitors, an output terminal, and means for commonly connecting sources of said plurality of insulated-gate field-effect transistors to said output terminal.

Claim 18

The circuit according to claim 11, further comprising a reset insulated-gate field-effect transistor coupled between said output terminal and a terminal receiving a ground potential.

Claim 19

An output circuit comprising means for receiving an input signal, a drive node, means for receiving a power voltage, bootstrap circuit means responsive to said input signal for operatively raising a potential at said drive node above said power voltage, the raised potential being maintained capacitively and having a tendency to be reduced responsive to an elapse of time, an insulated-gate field-effect transistor having a drain coupled to receive said power voltage and a gate coupled to said drive node, an output terminal, a capacitor having a first terminal coupled to said drive node, means for generating a repetitive sequence of signals, and means for supplying a second terminal of said capacitor with said repetitive signals, whereby a level of said raised potential is maintained above said power voltage.

Claim 20

An output circuit comprising means for receiving an input signal, a drive node, means for receiving a power voltage, bootstrap circuit means responsive to said input signal for operatively raising a potential at said drive node above said power voltage, the raised potential being maintained capacitively and having a tendency to be reduced responsive to an elapse of time, an insulated-gate field-effect transistor having a drain coupled to receive said power voltage and a gate coupled to said drive node, an output terminal, a capacitor having a first terminal coupled to said drive node, means for generating a repetitive sequence of signals, and means for supplying a second terminal of said capacitor with said repetitive signals, whereby a level of said raised potential is maintained above said power voltage.