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EP0035408A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Circuit for maintaining the potential of a node of a MOS dynamic circuit

Assignee: Fujitsu Ltd
•
Filing: 1981-03-03
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Granted: —
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Expires: 2001-03-03
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Abstract

Abstract A circuit for maintaining the potential of a node (ND) of a MOS dynamic circuit (1) includes a repetitive charging circuit (4) which comprises a circuit (41, 42, 45) to supply a charging current to the node from a point the potential of which is raised higher than a supply source voltage (V<sub>cc</sub>) during a predetermined period by the application of a clock signal (S<sub>3</sub>) whereby the potential of the node is maintained at a predetermined potential (V<sub>nd</sub>) higher than the supply source voltage, without supplying a steady current to the node, until a reset signal (S<sub>2</sub>) is applied to the MOS dynamic circuit. The circuit comprises a number of MOS field-effect transistors (41, 42) and a MOS capacitor (45), the higher potential point being formed at a connecting point of the electrodes of the MOS field-effect transistors and one electrode of the MOS capacitor.

Inventors

  • 👤 Tomio Nakano

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-27 19:59
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 118 words
A circuit for maintaining the potential of a node (ND) of a MOS dynamic circuit (1) with a repetitive charging circuit (4), characterised in that the repetitive charging circuit comprises means (41, 42, 45) to supply a charging current to the node from a point the potential of which point is raised higher than a supply source voltage (V cc ) during a predetermined period by the application of a clock signal (S 3 ), whereby the potential of the node is maintained at a predetermined potential (V nd ) higher than the supply source voltage, without supplying a steady current to the node, until a reset signal (S 2 ) is applied to the MOS dynamic circuit.
Claim 2
Dependent Claim 118 words
A circuit for maintaining the potential of a node (ND) of a MOS dynamic circuit (1) with a repetitive charging circuit (4), characterised in that the repetitive charging circuit comprises means (41, 42, 45) to supply a charging current to the node from a point the potential of which point is raised higher than a supply source voltage (V cc ) during a predetermined period by the application of a clock signal (S 3 ), whereby the potential of the node is maintained at a predetermined potential (V nd ) higher than the supply source voltage, without supplying a steady current to the node, until a reset signal (S 2 ) is applied to the MOS dynamic circuit.
Claim 3
Dependent Claim 60 words
A circuit as claimed in Claim 1, characterised in that the means to supply a charging current to the node (ND) comprises a number of MOS field-effect transistors (41, 42) and a MOS capacitor (45), the higher potential point being formed at a connecting point of the electrodes of the MOS field-effect transistors and one electrode of the MOS capacitor.
Claim 4
Dependent Claim 27 words
A circuit as claimed in Claim 2, characterised in that a clock signal (S 4 ) is applied to the other electrode of the MOS capacitor (45).
Claim 5
Dependent Claim 34 words
A circuit as claimed in Claim 2 or Claim 3, characterised in that a reverse current preventing transistor (43) is connected between the higher potential point and one of the MOS field-effect transistors (42).
Claim 6
Dependent Claim 35 words
A circuit as claimed in Claim 2 or Claim 3, characterised in that a reverse current preventing transistor (44) is connected between the voltage source (V ) and one of the NOS field-effect transistors (41).
Claim 7
Dependent Claim 33 words
A circuit as claimed in Claim 2 or Claim 3, characterised in that a clock pulse signal (S 4 ) is supplied to the gate of one of the MOS field-effect transistors (42).
Claim 8
Dependent Claim 40 words
A circuit as claimed in Claim 3, characterised in that the clock signal (S 4 ) is obtained from an oscillator provided outside a chip on which the MOS dynamic circuit (1) and the repetitive charging circuit (4) are arranged.
Claim 9
Dependent Claim 47 words
A circuit as claimed in Claim 3, characterised in that the clock signal (S 4 ) is obtained from an oscillator included in a substrate bias voltage generator provided on a chip on which the MOS dynamic circuit (1) and the repetitive charging circuit (4) are arranged.

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