EP0045133A2
Expired / Lapsed
EP
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Bootstrap driver circuits for an MOS memory
Assignee: Inmos Corp
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Filing: 1981-06-25
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Granted: —
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Expires: 2001-06-25
Abstract
Abstract A high speed, low power bootstrap driver is disclosed for use in an MOS memory. The basic driver includes first and second enhancement mode transistors (12, 14) for receiving a digital input (16). The drain of the first transistor (12) is coupled to a high impedance depletion mode transistor (22), and the drain of the latter transistor is coupled to the source of a low impedance transistor (26). Another enhancement mode transistor (30) is coupled via its sources to the drain of the second enhancement mode transistor (14) and is coupled via its gate to the drain of the first enhancement mode transistor (12). A capacitor (34) is connected between the drain of the high impedance transistor (22) and the drain of the second enhancement mode transistor (14). When a low level input is received, the drain of the first enhancement mode transistor (12) is rapidly bootstrapped to a high level voltage above the positive power supply for use as an output signal (18).
Inventors
- 👤 Rahul Sud
- 👤 Kim Carver Hardee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 07:11
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01735; G; G11; G11C; G11C7/00; G11C7/12; G11C8/00; G11C8/08; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
322 words
A bootstrap driver, characterised by first and second enhancement mode transistors (12,14) each having a gate for receiving a digital input signal (16) which varies between high and low levels, said transistors being adapted to turn on and off in response to high and low levels, respectively, of the input signal; a high impedance depletion mode transistor (22) having its gate coupled to its source and its source coupled to the drain of said first transistor (12) so as to define a first node (20) at their mutual connection; a low impedance transistor (26) having its drain coupled to a source (V cc ) of operating voltage and its source coupled to the drain of said high impedance transistor (22) to define a second node (24) between said high impedance transistor and said low impedance transistor, the latter transistor receiving a voltage at its gate for coupling a high level voltage to said second node; a third enhancement mode transistor (30) having its drain coupled to a source (V ) of operating voltage, having its source coupled to the drain of said second enhancement mode transistor (14) to define a third node (28) and having its gate ' connected to said first node (20); and a capacitor (34) connected between said second and third nodes (24,28) such that, when the input signal goes low, said first and second enhancement mode transistors (12,14) turn off, said first node (20)'is pulled high, said third enhancement mode transistor (30) turns on, said third node (28) is pulled high, the voltage transition at said third node is capacitively coupled to said second node (24) and via said high impedance transistor (22) back to the gate of said third enhancement mode transistor (30) so as to increase the conduction in said third enhancement mode transistor (30) and pull said first and third nodes (20,28) to a high level for use as one or more inverted output signals.
Claim 2
Dependent Claim
322 words
A bootstrap driver, characterised by first and second enhancement mode transistors (12,14) each having a gate for receiving a digital input signal (16) which varies between high and low levels, said transistors being adapted to turn on and off in response to high and low levels, respectively, of the input signal; a high impedance depletion mode transistor (22) having its gate coupled to its source and its source coupled to the drain of said first transistor (12) so as to define a first node (20) at their mutual connection; a low impedance transistor (26) having its drain coupled to a source (V cc ) of operating voltage and its source coupled to the drain of said high impedance transistor (22) to define a second node (24) between said high impedance transistor and said low impedance transistor, the latter transistor receiving a voltage at its gate for coupling a high level voltage to said second node; a third enhancement mode transistor (30) having its drain coupled to a source (V ) of operating voltage, having its source coupled to the drain of said second enhancement mode transistor (14) to define a third node (28) and having its gate ' connected to said first node (20); and a capacitor (34) connected between said second and third nodes (24,28) such that, when the input signal goes low, said first and second enhancement mode transistors (12,14) turn off, said first node (20)'is pulled high, said third enhancement mode transistor (30) turns on, said third node (28) is pulled high, the voltage transition at said third node is capacitively coupled to said second node (24) and via said high impedance transistor (22) back to the gate of said third enhancement mode transistor (30) so as to increase the conduction in said third enhancement mode transistor (30) and pull said first and third nodes (20,28) to a high level for use as one or more inverted output signals.
Claim 3
Dependent Claim
53 words
A bootstrap driver as set forth in claim 1 further characterised in that each of said transistors has a gate width to length ratio, and wherein the width to length ratio of said high impedance depletion mode transistor is much smaller than the corresponding ratios of the other transistors in the bootstrap driver.
Claim 4
Dependent Claim
32 words
A bootstrap driver as set forth in claim 1 further characterised in that said low impedance transistor is adapted to receive a control signal at its gate for power gating the driver.
Claim 5
Dependent Claim
21 words
A bootstrap driver as set forth in claim 1 characterised in that said low impedance transistor is an enhancement mode transistor.
Claim 6
Dependent Claim
38 words
A driver as set forth in claim 1 further characterised by a charge pump coupled to said second node for pumping current thereto so as to maintain the voltage at said second node at a relatively high level.
Claim 7
Dependent Claim
136 words
A bootstrap driver as set forth in claim 1 further characterised by a plurality of grounded- source transistors whose gates are adapted to receive memory address signals and whose drains are coupled to a common node, and means for coupling said common node to the source of. said first enhancement mode transistor, and transistor means coupled to said common node for inverting the signal thereat and for coupling the latter inverted signal as a delayed input signal to the gates of said first and second enhancement mode transistors such that said second transistor remains momentarily conductive to provide a discharge path for said third node in response to a low level memory address signal in order to maintain a differential voltage across said capacitor, whereby the bootstrap driver is adapted to operate as an address decoder.
Claim 8
Dependent Claim
78 words
A bootstrap driver as set forth in claim 6 further characterised by an additional enhancement mode transistor having its gate coupled to said first node and its source coupled to said common node such that, when a low level memory address signal occurs, the latter transistor is turned on for holding said common node at a high voltage level, and for maintaining said first transistor in an off condition to isolate said common node from said first node.
Claim 9
Dependent Claim
24 words
A bootstrap driver as set forth in claim 7 further characterised by a charge pump coupled to said second node for pumping current thereto.
Claim 10
Dependent Claim
39 words
A bootstrap driver as set forth in claim 1 further characterised in that said digital input signal is derived from a plurality of memory address bits and an output signal from the driver corresponds to a decoded memory address.
Claim 11
Dependent Claim
163 words
A bootstrap driver as set forth in claim 4 -further characterised by a dynamic Schmitt trigger input stage for deriving said digital input signal, said input stage including a fourth enhancement mode transistor having a grounded source and a gate adapted to receive a pulse input, a fifth enhancement mode transistor having its source coupled to the drain of said fourth transistor and its gate coupled to the gate of said fourth transistor; a sixth enhancement mode transistor having its source coupled to the drain of said fifth transistor, its gate adapted to receive a pre-charge signal, and its drain coupled to a source of operating voltage; a seventh enhancement mode transistor having its drain coupled to the source of operating voltage, its source coupled to the drain of said fourth transistor and its gate coupled to the source of said sixth transistor; and means for coupling the gate of.said seventh transistor to the gates of said first and second enhancement mode transistors.
Claim 12
Dependent Claim
22 words
A bootstrap driver as set forth in claim 1 further characterised in that said low impedance transistor is a depletion mode transistor.
Claim 13
Dependent Claim
94 words
A bootstrap driver as set forth in claim 11 further characterised in that the drain of said first enhancement mode transistor is coupled to said first node by a fourth enhancement mode transistor, and including means for coupling the voltage at said first node to an output terminal for use as an output signal, and means for coupling low-going digital signals to said first, second and fourth enhancement mode transistors and to said low impedance transistor so that the voltage at said first node and said output signal are bootstrapped to a high level.
Claim 14
Dependent Claim
166 words
A bootstrap driver as set forth in claim 12 further characterised by a timing circuit for developing a first low-going ditigal signal and a second, delayed low-going digital signal, means for coupling the first digital signal to said fourth transistor so as to turn the latter transistor off, and means for coupling the delayed digital signal to the gates of said first and second enhancement mode transistors and to the low impedance transistor so that, when said fourth enhancement mode transistor is turned off, the voltage at said first node begins to rise, the delayed digital signal turns off the first and second enhancement mode transistors and reduces conduction of said low impedance transistor, the third enhancement mode transistor is rendered conductive, the voltage at the second node is bootstrapped to a high level for completely turning off the low impedance transistor, and said high impedance transistor couples the high level voltage from said second node to said first node for driving the output signal high.
References Cited (Backward Citations)
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