High voltage clock generator

Claim 2

A high voltage clock generator comprising: a first clock generator to charge a load capacitance to a first voltage level; a bootstrap capacitance having a base plate and a top plate; an isolation and precharge circuit to charge the top plate of the bootstrap capacitance at a time prior to driving the load capacitance to a second voltage level; and a second clock generator to drive the base plate of the bootstrap capacitance such that the load capacitance is driven to the second voltage level.

Claim 3

The high voltage clock generator of claim 1 wherein the first clock generator comprises: a first MOSFET with its source grounded, and its gate tied to a precharge signal; a second MOSFET with its source tied to the drain of the first MOSFET, its drain tied to a voltage supply, and its gate tied to a first clock signal; a third MOSFET with its gate tied to the drain of the first MOSFET and its source grounded; a fourth MOSFET with its source tied to the drain of the third MOSFET, its drain tied to a voltage supply, and its gate tied to a precharge signal; a fifth MOSFET with its source tied to the drain of the third MOSFET, and its gate tied to a voltage supply; a sixth MOSFET with its drain tied to a first clock signal and its gate tied to the drain of the fifth MOSFET; a seventh MOSFET with its source grounded and its gate tied to the drain of the third MOSFET; a capacitance with a first terminal tied to the source of the sixth MOSFET and a second terminal tied to the drain of the seventh MOSFET; an eighth MOSFET with its gate tied to the source of the sixth MOSFET, its source tied to the second terminal of the capacitance, and its drain tied to a supply voltage; a ninth MOSFET with its gate tied to the drain of the third MOSFET and its source grounded; a tenth MOSFET with its source tied to the drain of the ninth MOSFET and its drain tied to the isolation and precharge circuit in the bootstrap capacitance; and an eleventh MOSFET with its drain tied to the gate of the tenth MOSFET and to the isolation and precharge circuit, its source grounded and its gate tied to a precharge signal.

Claim 4

The high voltage clock generator of claim 2 wherein the isolation and precharge circuit comprises: a twelfth MOSFET with itsdrain tied to a supply voltage and its gate tied to a precharge signal; a thirteenth MOSFET with its drain tied to the source of the twelfth MOSFET, its gate tied to the second clock generator, and its source grounded; a capacitance with a first terminal tied to a first clock signal, and a second terminal tied to the source of the twelfth MOSFET; a first depletion MOSFET with its gate tied to the source of the twelfth MOSFET, and its source and drain tied to the first clock generator; and a second depletion MOSFET with its drain tied to a supply voltage, its gate tied to the source of the twelfth MOSFET, and its source tied to the bootstrap capacitance and the first clock generator.

Claim 5

The high voltage clock generator of claim 1 wherein the second clock generator comprises: a first MOSFET with its source grounded, and its gate tied to a precharged signal; a second MOSFET with its source tied to the drain of the first MOSFET, its drain tied to a voltage supply, and its gate tied to a first clock signal; a third MOSFET with its gate tied to the drain of the first MOSFET and its source grounded; a fourth MOSFET with its source tied to the drain of the third MOSFET, its drain tied to a voltage supply, and its gate tied to a precharge signal; a fifth MOSFET with its source tied to the drain of the third MOSFET, and its gate tied to a voltage supply; a sixth MOSFET with its drain tied to a first clock signal and its gate tied to the drain of the fifth MOSFET; a seventh MOSFET with its source grounded and its gate tied to the drain of the third MOSFET; a capacitance with a first terminal tied to the source of the sixth MOSFET and a second terminal tied to the drain of the seventh MOSFET; an eighth MOSFET with its gate tied to the source of the sixth MOSFET, its source tied to the second terminal of the capacitance, and its drain tied to a supply voltage; a ninth MOSFET with its gate tied to the drain of the third MOSFET and its source grounded; a tenth MOSFET with its drain tied to a supply voltage and its gate tied to the first terminal of the capacitance; and an eleventh MOSFET with its drain tied to the gate of the tenth MOSFET and to the isolation and precharge circuit, its source grounded, and its gate tied to a precharge signal.

Claim 6

The high voltage clock generator of claim 1 wherein the isolation and precharge circuit comprises: a first MOSFET with its drain tied to a supply voltage and its gate tied to a precharge signal; a second MOSFET with its drain tied to the source of the first MOSFET, its gate tied to the second clock generator, and its source grounded; a capacitance with a first terminal tied to a first clock signal, and a second terminal tied to the source of the first MOSFET; a first depletion MOSFET with its gate tied to the source of the first MOSFET, and its source and drain tied to the first clock generator; and a second depletion MOSFET with its drain tied to a supply voltage, its gate tied to the source of the first MOSFET, and its source tied to the bootstrap capacitance and the first clock generator.

Claim 7

The high voltage clock generator of claim 1 wherein the first clock generator and second clock generator are similar units.

Claim 8

The high voltage clock generator of claim 6 wherein the isolation and precharge circuit comprises: a first MOSFET with its drain tied to a supply voltage and its gate tied to a precharge signal; a second MOSFET with its drain tied to the source of the first MOSFET, its gate tied to the second clock generator, and its source grounded; a capacitance with a first terminal tied to a first clock signal, and a second terminal tied to the source of the first MOSFET; a first depletion MOSFET with its gate tied to the source of the first MOSFET, and its source and drain tied to the first clock generator; and a second depletion MOSFET with its drain tied to a supply voltage, its gate tied to the source of the first MOSFET, and its source tied to the bootstrap capacitance and the first clock generator.

Claim 9

A high voltage clock generator comprising: a first MOSFET with its source grounded, and its gate tied to a precharge signal; a second MOSFET with its source tied to the drain of the first MOSFET, its drain tied to a voltage supply, and its gate tied to a first clock signal; a third MOSFET with its gate tied to the drain of the first MOSFET and its source grounded; a fourth MOSFET with its source tied to the drain of the third MOSFET, its drain tied to a voltage supply, and its gate tied to a precharge signal; a fifth MOSFET with its source tied to the drain of the third MOSFET, and its gate tied to a voltage supply; a sixth MOSFET with its drain tied to a first clock signal and its gate tied to the drain of the fifth MOSFET; a seventh MOSFET with its source grounded and its gate tied to the drain of the third MOSFET; a capacitance with a first terminal tied to the source of the sixth MOSFET and a second terminal tied to the drain of the seventh MOSFET; an eighth MOSFET with its gate tied to the source of the sixth MOSFET, its source tied to the second terminal of the capacitance, and its drain tied to a supply voltage; a ninth MOSFET with its gate tied to the drain of the third MOSFET and its source grounded; a tenth MOSFET with its source tied to the drain of the ninth MOSFET and its drain tied to the isolation and precharge circuit and bootstrap capacitance; an eleventh MOSFET with its drain tied to the gate of the tenth MOSFET and to the isolation and precharge circuit, its source grounded, and its gate tied to a precharge signal; a bootstrap capacitance to drive the load capacitance to a second voltage level; a twelfth MOSFET with its drain tied to a supply voltage and its gate tied to a precharge signal; a thirteenth MOSFET with its drain tied to the source of the twelfth MOSFET, its gate tied to the second clock generator, and its source grounded; a second capacitance with a first terminal tied to a first clock signal, and a second terminal tied to the source of the twelfth MOSFET; a first depletion MOSFET with its gate tied to the source of the twelfth MOSFET, and its source and drain tied to the first clock generator; a second depletion MOSFET with its drain tied to a supply voltage, its gate tied to the source of the twelfth MOSFET, and its source tied to the bootstrap capacitance and the first clock generator; a fourteenth MOSFET with its source grounded, and its gate tied to a precharge signal; a fifteenth MOSFET with its source tied to the drain of the fourteenth MOSFET, its drain tied to a voltage supply, and its gate tied to a first clock signal; a sixteenth MOSFET with its gate tied to the drain of the fourteenth MOSFET and its source grounded; a seventeenth MOSFET with its source tied to the drain of the sixteenth MOSFET, its drain tied to a voltage supply, and its gate tied to a precharge signal; an eighteenth MOSFET with its source tied to the drain of the sixteenth MOSFET, and its gate tied to a voltage supply; a nineteenth MOSFET with its drain tied to a first clock signal and its gate tied to the drain of the eighteenth MOSFET; a twentieth MOSFET with its source grounded and its gate tied to the drain of the sixteenth MOSFET; a third capacitance with a first terminal tied to the source of the nineteenth MOSFET and a second terminal tied to the drain of the twentieth MOSFET; a twenty-first MOSFET with its gate tied to the source of the nineteenth MOSFET, its source tied to the second terminal of the third capacitance, and its drain tied to a supply voltage; a twenty-second MOSFET with its gate tied to the drain of the sixteenth MOSFET and its source grounded; a twenty-third MOSFET with its drain tied to a supply voltage and its gate tied to the first terminal of the third capacitance; and a twenty-fourth MOSFET with its drain tied to the gate of the twenty-third MOSFET, its source grounded, and its gate tied to a precharge signal.

Claim 10

A high voltage clock generator comprising: a first MOSFET with its source grounded, and its gate tied to a precharge signal; a second MOSFET with its source tied to the drain of the first MOSFET, its drain tied to a voltage supply, and its gate tied to a first clock signal; a third MOSFET with its gate tied to the drain of the first MOSFET and its source grounded; a fourth MOSFET with its source tied to the drain of the third MOSFET, its drain tied to a voltage supply, and its gate tied to a precharge signal; a fifth MOSFET with its source tied to the drain of the third MOSFET, and its gate tied to a voltage supply; a sixth MOSFET with its drain tied to a first clock signal and its gate tied to the drain of the fifth MOSFET; a seventh MOSFET with its source grounded and its gate tied to the drain of the third MOSFET; a capacitance with a first terminal tied to the source of the sixth MOSFET and a second terminal tied to the drain of the seventh MOSFET; an eighth MOSFET with its gate tied to the source of the sixth MOSFET, its source tied to the second terminal of the capacitance, and its drain tied to a supply voltage; a ninth MOSFET with its gate tied to the drain of the third MOSFET and its source grounded; a tenth MOSFET with its source tied to the drain of the ninth MOSFET and its drain tied to the isolation and precharge circuit and bootstrap capacitance; an eleventh MOSFET with its drain tied to the gate of the tenth MOSFET and to the isolation and precharge circuit, its source grounded, and its gate tied to a precharge signal; a bootstrap capacitance to drive the load capacitance to a second voltage level; a twelfth MOSFET with its drain tied to a supply voltage and its gate tied to a precharge signal; a thirteenth MOSFET with its drain tied to the source of the twelfth MOSFET, its gate tied to the second clock generator, and its source grounded; a second capacitance with a first terminal tied to a first clock signal, and a second terminal tied to the source of the twelfth MOSFET; a first depletion MOSFET with its gate tied to the source of the twelfth MOSFET, and its source and drain tied to the first clock generator; a second depletion MOSFET with its drain tied to a supply voltage, its gate tied to the source of the twelfth MOSFET, and its source tied to the bootstrap capacitance and the first clock generator; a fourteenth MOSFET with its source grounded, and its gate tied to a precharge signal; a fifteenth MOSFET with its source tied to the drain of the fourteenth MOSFET, its drain tied to a voltage supply, and its gate tied to a first clock signal; a sixteenth MOSFET with its gate tied to the drain of the fourteenth MOSFET and its source grounded; a seventeenth MOSFET with its source tied to the drain of the sixteenth MOSFET, its drain tied to a voltage supply, and its gate tied to a precharge signal; an eighteenth MOSFET with its source tied to the drain of the sixteenth MOSFET, and its gate tied to a voltage supply; a nineteenth MOSFET with its drain tied to a first clock signal and its gate tied to the drain of the eighteenth MOSFET; a twentieth MOSFET with its source grounded and its gate tied to the drain of the sixteenth MOSFET; a third capacitance with a first terminal tied to the source of the nineteenth MOSFET and a second terminal tied to the drain of the twentieth MOSFET; a twenty-first MOSFET with its gate tied to the source of the nineteenth MOSFET, its source tied to the second terminal of the third capacitance, and its drain tied to a supply voltage; a twenty-second MOSFET with its gate tied to the drain of the sixteenth MOSFET and its source grounded; a twenty-third MOSFET with its drain tied to a supply voltage and its gate tied to the first terminal of the third capacitance; and a twenty-fourth MOSFET with its drain tied to the gate of the twenty-third MOSFET, its source grounded, and its gate tied to a precharge signal.