Pulse enhancement circuit for digital integrated circuit

Claim 1

In an integrated digital MOS semiconductor circuit with a first circuit section serving as a pulse generator (S1) and a second circuit section (S2) serving as a pulse receiver, the input of which is controlled by two-level pulses supplied in part by first pulse signal (φ 0 ) from the first circuit section, the first pulse signal being fed at the same time via the source-drain path of a first transistor (T1) to a first terminal of a first capacitor (C1) and further, via a second transistor (T2) to a first terminal of a second capacitor (C2) which is connected via a third transistor (T3) to a supply potential (V CC ) which operates together with a reference potential (v SS ) to supply the first circuit section (S1) and the second circuit section (S2), the gate of the second transistor (T2) being connected to the source terminal of the first transistor (T1) and to the first terminal of the first capacitor (C1); said transistors (T1, T2, T3) being latching MOS field-effect transistors; the second terminals of the first capacitor (C1) and of the second capacitor (C2) each receiving digital pulse signals (φ 1 , φ 2 ) supplied by a third circuit section; said third circuit section being responsive to the pulse signal of said first circuit section; the pulse pulse signal φ 1 being applied to the second terminal of the first capacitor (C1) and the pulse signal φ 2 being applied to the second terminal of the second capacitor (C2) and wherein the pulse signal φ 0 supplied by the first circuit section (S1) as well as the digital pulse signals φ 1 and φ 2 have simultaneous trailing edges, the leading edge of the pulse signal φ 0 delivered by the first circuit section (S1) occurring before the leading edges of the pulse signals φ 1 and φ 2 , and the leading edge of the pulse signal φ 2 occurring no sooner than the leading edge of the pulse signal φ 1 , the improvement comprising that the gate of the first transistor (T1) is connected to the supply potential (V CC ) through two further transistors (T5, T6) of the same type as the aforesaid transistors (T1 to T3); that a third capacitor (C4) is connected between the gate and the drain of the first transistor (T1); and that the gate of the first transistor (T1) is connected to the source terminals of the two further transistors (T5, T6) and to the gate of one of said further transistors (T6), the remaining terminals of said two further transistors (T5, T6) being connected to the supply potential (V CC ).