Electrically erasable programmable read only memory

Claim 2

A floating gate electrically erasable programmable read only memory cell comprising: a semiconductor body having a major surface, said body having first and second regions of a first conductivity type and a first region of a second conductivity type, all adjacent to said first major surface, said first region of said second conductivity type lying between said first and second regions of said first conductivity type; control gate means overlying a portion of said first region of said second conductivity type and separated therefrom by a dielectric material, electrical conditions on said control gate means being capable of affecting the effective electrical conductivity in said first region of said second conductivity type; and floating gate means having a coupling region, a control region, and a tunneling region, said coupling region overlying said control gate means and being separated therefrom by said dielectric material, said control region being adjacent to said first region of said second conductivity type and separated therefrom by said dielectric material, electrical conditions on said control region being capable of affecting the effective electrical conductivity in said first region of said second conductivity type, and said tunneling region being adjacent to said first region of said first conductivity type and separated therefrom by said dielectric material, said tunneling region being separated from said major surface by a distance which is substantially smaller than that separating said control region from said major surface.

Claim 3

The memory cell of claim 1 wherein said semiconductor body comprises silicon.

Claim 4

The memory cell of claim 2 wherein said control gate means and said floating gate means each comprise polycrystalline silicon.

Claim 5

The memory cell of claim 1 further comprising: a third region of said first conductivity type located within said semiconductor body and adjacent to said major surface; a second region of said second conductivity type located within said semiconductor body and adjacent to said major surface, said second region of said second conductivity type lying between said first and third regions of said first conductivity type; and select gate means adjacent to said second region of said second conductivity type and separated therefrom by said dielectric material, electrical conditions on said select gate means being capable of affecting the effective electrical conductivity in said second region of said second conductivity type.

Claim 6

The memory cell of claim 4 wherein said semiconductor body comprises silicon.

Claim 7

The memory cell of claim 5 wherein said select gate means, said floating gate means, and said control gate means all comprise polycrystalline silicon.

Claim 8

The memory cell of claim 6 wherein said first conductivity type is n type and said second conductivity type is p type.

Claim 9

A memory cell array comprising: a semiconductor body having a major surface; a plurality of bit line means, each of said bit line means being electrically conductive; a plurality of word line means, each of said word line means being electrically conductive; a plurality of program line means each of said program line means being electrically conductive; and a plurality of memory cell means each of said memory cell means comprising: first, second, and third regions of a first conductivity type lying within said semiconductor body and adjacent to said major surface, each of said third regions of said first conductivity type being electrically connected to one of said bit line means; first and second regions of a second conductivity type lying within said semiconductor body and adjacent to said major surface, said first region of said second conductivity type being located between said first and second regions of said first conductivity type and said second region of said second conductivity type being located between said first and third regions of said first conductivity type; control gate means overlying said first region of said second conductivity type and separated therefrom by a dielectric material, electrical conditions on said control gate means being capable of affecting the effective electrical conductivity in said first region of said second conductivity type, each of said control gate means being electrically connected to one of said program line means; floating gate means having a coupling region, a control region, and a tunneling region, said coupling region overlying said control gate means and being separated therefrom by said dielectric material, said control region being adjacent to said first region of said second conductivity type and separated therefrom by said dielectric material, electrical conditions on said control region being capable of affecting the effective electrical conductivity in said first region of said second conductivity type, said tunneling region being adjacent to said first region of said first conductivity type and separated therefrom by said dielectric material, said tunneling region being separated from said major surface by a distance which is substantially smaller than that separating said control region from said major surface; and select gate means adjacent to said second region of said second conductivity type and separated therefrom by said dielectric material, each of said select gate means being electrically connected to one of said word line means.

Claim 10

A memory cell array comprising: a semiconductor body having a major surface; a plurality of bit line means, each of said bit line means being electrically conductive; a plurality of word line means, each of said word line means being electrically conductive; a plurality of program line means each of said program line means being electrically conductive; and a plurality of memory cell means each of said memory cell means comprising: first, second, and third regions of a first conductivity type lying within said semiconductor body and adjacent to said major surface, each of said third regions of said first conductivity type being electrically connected to one of said bit line means; first and second regions of a second conductivity type lying within said semiconductor body and adjacent to said major surface, said first region of said second conductivity type being located between said first and second regions of said first conductivity type and said second region of said second conductivity type being located between said first and third regions of said first conductivity type; control gate means overlying said first region of said second conductivity type and separated therefrom by a dielectric material, electrical conditions on said control gate means being capable of affecting the effective electrical conductivity in said first region of said second conductivity type, each of said control gate means being electrically connected to one of said program line means; floating gate means having a coupling region, a control region, and a tunneling region, said coupling region overlying said control gate means and being separated therefrom by said dielectric material, said control region being adjacent to said first region of said second conductivity type and separated therefrom by said dielectric material, electrical conditions on said control region being capable of affecting the effective electrical conductivity in said first region of said second conductivity type, said tunneling region being adjacent to said first region of said first conductivity type and separated therefrom by said dielectric material, said tunneling region being separated from said major surface by a distance which is substantially smaller than that separating said control region from said major surface; and select gate means adjacent to said second region of said second conductivity type and separated therefrom by said dielectric material, each of said select gate means being electrically connected to one of said word line means.

Claim 11

The memory cell array of claim 8 wherein said semiconductor body comprises silicon.

Claim 12

The memory cell array of claim 9 wherein said control gate means, said floating gate means, and said select gate means all comprise polycrystalline silicon.

Claim 13

The memory cell array means of claim 10 wherein said first conductivity type is n type and said second conductivity type is p type.