Electrically alterable nonvolatile floating gate memory device

Claim 1

An array of nonvolatile floating gate memory devices arranged in rows and columns in a body of semiconductor material of a first conductivity type, alternate first and second doped regions of a second conductivity type arranged in columns embedded in the semiconductor body and spaced one from the other to define a channel region therebetween, a plurality of floating gate members in rows insulated from the substrate, each of the plurality of floating gate members defining a row having its one end thereof disposed over a respective channel region to define a first capacitance between the floating gate member and the body of the semiconductor material, the improvement comprising: a plurality of rows of conductive layers, the layer of each row insulated from and aligned with the floating gate members in a given row to define a second capacitance between the conductive layer and the overlying floating gate member; and an extended floating gate portion affixed to the other end of the floating gate member and extending therefrom over a first doped region associated with the respective channel region of one memory device to an adjacent second doped region of the next adjacent memory device to define a third capacitance between the other end of the floating gate member and to the adjacent doped region whereby, when a first source of potential is applied to the first and second regions and the body of semiconductor material and a second source of potential is applied to the adjacent doped region and a conductive layer, the second and third capacitances are effectively in parallel.