Electrically programmable non-volatile memory

Claim 2

An electrically programmable memory disposed on a substrate including: a plurality of electrically programmable memory cells formed on the surface of said substrate each having at least one region disposed in said substrate, a charge storing region and a control gate; charge generation means formed on said surface of said substrate for causing a charge imbalance in said substrate such that charge is present for charging any one of said plurality of said cells; and, electrical means coupled to said cells for selectively applying potentials to said cells such that said charge is caused to accelerate towards at least one of said charge storing regions and to become trapped therein, whereby a plurality of cells may be programmed from a single source of charge formed on said substrate.

Claim 3

The memory defined by claim 1 wherein said charge generation means comprises a forward biased junction disposed in said substrate from said surface.

Claim 4

The memory defined by claim 1 wherein said charge generation means comprises a metal-oxide-semiconductor device formed on said surface of said substrate which is in saturation for programming.

Claim 5

The memory defined by claim 1 wherein said charge generation means comprises hole injection means formed on said surface for injecting holes into said substrate and a source of electrons which provides electrons in response to said injected holes.

Claim 6

The memory defined by claim 4 wherein said source of electrons is an n-type region disposed in said substrate from said surface said n-type region being coupled to ground.

Claim 7

The memory defined by claim 1 wherein said charge generation means comprises a charge injection capacitor.

Claim 8

The memory defined by claim 6 wherein said charge injection capacitor includes a region in said substrate coupled to a load device and a gate coupled to a pulse generator.

Claim 9

An electrically programmable memory disposed on a substrate including: a plurality of electrically programmable memory cells formed on the surface of said substrate each having at least one region disposed in said substrate, a floating gate disposed above said surface of said substrate and a control gate disposed above said floating gate and insulated from said floating gate; a source of electrical charge, formed from said surface of said substrate for providing charge for programming said plurality of cells; electrical means for applying a first potential to at least a selected one of said regions and a second potential to a selected one of said control gates, said selected control gate being from the same selected cell as said selected region, such that charge is sufficiently accelerated towards said selected cell to overcome the barrier between said floating gate and substrate and become stored in said floating gate, whereby a plurality of cells may be selectively charged from a single source of charge.

Claim 10

An electrically programmable memory disposed on a substrate including: a plurality of electrically programmable memory cells formed on the surface of said substrate each having at least one region disposed in said substrate, a floating gate disposed above said surface of said substrate and a control gate disposed above said floating gate and insulated from said floating gate; a source of electrical charge, formed from said surface of said substrate for providing charge for programming said plurality of cells; electrical means for applying a first potential to at least a selected one of said regions and a second potential to a selected one of said control gates, said selected control gate being from the same selected cell as said selected region, such that charge is sufficiently accelerated towards said selected cell to overcome the barrier between said floating gate and substrate and become stored in said floating gate, whereby a plurality of cells may be selectively charged from a single source of charge.

Claim 11

The memory defined by claim 8 wherein said second potential is greater than said first potential.

Claim 12

The memory defined by claim 9 wherein said second potential exceeds said first potential by at least the threshold voltage of said cells.

Claim 13

The memory defined by claim 10 wherein said source of electrical charge comprises a forward biased junction.

Claim 14

The memory defined by claim 10 wherein said source of electrical charge comprises a metal-oxide-semiconductor device which is in saturation.

Claim 15

The memory defined by claim 10 wherein said source of electrical charge comprises hole injection means for injecting holes in said substrate and a source of electrons which provides electrons in response to said injected holes.

Claim 16

The memory device defined by claim 10 wherein said source of electrical charge comprises a charge injection capacitor.

Claim 17

The memory defined by claim 14 wherein said charge injection capacitor includes a region in said substrate coupled to a load device and a gate coupled to a pulse generator.

Claim 18

The memory defined by claim 8 wherein said cells are coupled in series pairs, with a common substrate region disposed between each pair of cells.

Claim 19

The memory defined by claim 16 wherein said regions associated with said pairs of cells are coupled to different bit lines in said memory and wherein said control gates of each pair of cells are coupled to different word lines in said memory.

Claim 20

An electrically programmable and electrically erasable memory disposed on a surface of a substrate including: a plurality of electrically programmable and electrically erasable memory cells formed on said surface each having two regions disposed in said substrate, a charge storing region and a control gate; charge generation means formed on said surface of said substrate for causing a charge imbalance in said substrate such that charge is present for charging any one of said plurality of cells; and, electrical means coupled to said cells for selectively applying potentials to said cells such that charge is caused to accelerate towards at least one of said cells with sufficient energy to be trapped in said charge storing region of said cell, whereby a plurality of cells may be programmed from a single source of charge.

Claim 21

An electrically programmable and electrically erasable memory disposed on a surface of a substrate including: a plurality of electrically programmable and electrically erasable memory cells formed on said surface each having two regions disposed in said substrate, a charge storing region and a control gate; charge generation means formed on said surface of said substrate for causing a charge imbalance in said substrate such that charge is present for charging any one of said plurality of cells; and, electrical means coupled to said cells for selectively applying potentials to said cells such that charge is caused to accelerate towards at least one of said cells with sufficient energy to be trapped in said charge storing region of said cell, whereby a plurality of cells may be programmed from a single source of charge.

Claim 22

The memory defined by claim 18 wherein said charge storing region comprises a polysilicon floating gate.

Claim 23

The memory defined by claim 19 wherein in each of said cells, said floating gates is disposed over the channel defined by said regions and extends over one of said regions.

Claim 24

The memory defined by claim 20 wherein each of said floating gates is doped with an n-type dopant over said channel region and with a p-type dopant over said one of said regions.

Claim 25

The memory defined by claim 20 wherein each of said floating gates is n+ over said channel and n- over said one of said regions.

Claim 26

The memory defined by claim 20 wherein said cells are coupled into series pairs and wherein said one of said regions of each of said pairs are a common region between said cells.

Claim 27

The memory defined by claim 20 wherein said charge generation means comprises a charge injection capacitor.

Claim 28

The memory defined by claim 24 wherein said charge injection capacitor includes a region in said substrate coupled to a load device and a gate coupled to a pulse generator.

Claim 29

The memory defined by claim 20 wherein said charge generation means comprises a metal-oxide-semiconductor device disposed in said substrate which is in saturation.

Claim 30

The memory defined by claim 20 wherein said charge generation means comprises a forward biased junction disposed in said substrate.

Claim 31

The memory defined by claim 20 wherein said charge generation means comprises hole injection means and source of electrons which provide electrons in response to said injected holes.

Claim 32

In a memory which includes a plurality of electrically programmable memory cells fabricated on a surface of a substrate, a method for programming said cells comprising: generating a charge imbalance from said surface of said substrate such that excess electrons are present in the region of said plurality of cells; selectively applying potentials to said cells to cause said excess electrons to be accelerated towards at least a selected one of said cells with sufficient energy to program said cell; whereby a plurality of cells may be programmed from a single source of charge.

Claim 33

In a memory which includes a plurality of electrically programmable memory cells fabricated on a surface of a substrate, a method for programming said cells comprising: generating a charge imbalance from said surface of said substrate such that excess electrons are present in the region of said plurality of cells; selectively applying potentials to said cells to cause said excess electrons to be accelerated towards at least a selected one of said cells with sufficient energy to program said cell; whereby a plurality of cells may be programmed from a single source of charge.