US4586240A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vertical IGFET with internal gate and method for making same
Assignee: Fairchild Semiconductor Corp
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Filing: 1985-06-26
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Granted: 1986-05-06
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Expires: 2005-06-26
Abstract
Abstract A vertical IGFET comprising a substantially planar silicon wafer with a source electrode on one major surface and a drain electrode on the opposite major surface is disclosed. An insulated gate electrode, which includes a conductive finger portion surrounded by an insulating layer, is internally disposed in the silicon wafer such that a predetermined voltage applied to the gate electrode will regulate a current flow between the source and drain electrodes. The device is fabricated utilizing an epitaxial lateral overgrowth technique for depositing monocrystalline silicon over the insulated gate which is disposed on a silicon substrate.
Inventors
- 👤 Scott C. Blackstone
- 👤 Lubomir L. Jastrzebski
- 👤 John F. Corboy, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:43
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/63; H10D30/01; H10D30/021; H10D30/025; H10D30/635; H10D30/64; H10D30/66; H10D30/668; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/512; H10D64/513; Y; Y10; Y10S; Y10S148/00; Y10S148/019; Y10S148/123; Y10S148/126
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
132 words
A method for fabricating a vertical IGFET, comprising: providing a monocrystalline silicon substrate having first and second opposing major surfaces; forming a first oxide layer across the first surface; forming a pattern of doped polycrystalline silicon on the oxide layer; forming a second oxide layer on all exposed portions of the polycrystalline silicon so as to form an insulated gate; removing the first oxide layer from the first substrate surface in areas not covered by the insulated gate; depositing epitaxial silicon on the first substrate surface and the insulated gate, and terminating said epitaxial deposition after a surface which is substantially parallel to the first surface is formed; and providing source, drain and gate electrodes in ohmic contact with the epitaxial silicon surface, the second substrate surface, and the polycrystalline silicon, respectively.
Claim 2
Independent Claim
132 words
A method for fabricating a vertical IGFET, comprising: providing a monocrystalline silicon substrate having first and second opposing major surfaces; forming a first oxide layer across the first surface; forming a pattern of doped polycrystalline silicon on the oxide layer; forming a second oxide layer on all exposed portions of the polycrystalline silicon so as to form an insulated gate; removing the first oxide layer from the first substrate surface in areas not covered by the insulated gate; depositing epitaxial silicon on the first substrate surface and the insulated gate, and terminating said epitaxial deposition after a surface which is substantially parallel to the first surface is formed; and providing source, drain and gate electrodes in ohmic contact with the epitaxial silicon surface, the second substrate surface, and the polycrystalline silicon, respectively.
Claim 3
Dependent Claim
18 words
A method in accordance with claim 1, further comprising: doping the epitaxial silicon during the epitaxial silicon deposition.
Claim 4
Dependent Claim
25 words
A method in accordance with claim 1, further comprising: doping the epitaxial silicon and the substrate prior to providing the source, drain and gate electrodes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |