Diode load emitter coupled logic circuits

Claim 2

A gating circuit responsive to first and second complementary input signals from a signal source for generating first and second complementary output signals, said circuit comprising: first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second input signals, respectively, and collector terminals providing said first and second output signals, respectively; means coupled to the emitter terminals of the first and second switching transistors for generating a predetermined bias current; and first and second load means coupled between a power source and collector terminals of the first and second switching transistors, respectively, said first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal.

Claim 3

The circuit according to claim 1, wherein said bias current generating means includes means for varying the generated bias current in response to a control signal from a control signal source.

Claim 4

A gating circuit responsive to first and second complementary input signals from a first signal source and third and fourth complementary input signals from a second signal source for generating first and second complementary output signals, said circuit comprising: first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second input signals, respectively, and collector terminals providing said first and second output signals, respectively; third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said third and fourth input signals, respectively, and collector terminals coupled to the intercoupled emitter terminals of the first and second switching transistors and the output terminal of the second switching transistor, respectively; means coupled to the emitter terminals of the third and fourth switching transistors for generating a predetermined bias current; and first and second load means coupled between a power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal.

Claim 5

A gating circuit responsive to first and second complementary input signals from a first signal source and third and fourth complementary input signals from a second signal source for generating first and second complementary output signals, said circuit comprising: first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second input signals, respectively, and collector terminals providing said first and second output signals, respectively; third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said third and fourth input signals, respectively, and collector terminals coupled to the intercoupled emitter terminals of the first and second switching transistors and the output terminal of the second switching transistor, respectively; means coupled to the emitter terminals of the third and fourth switching transistors for generating a predetermined bias current; and first and second load means coupled between a power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal.

Claim 6

The circuit according to claim 3, wherein said bias current generating means includes means for varying the generated bias current in response to a control signal from a control signal source.

Claim 7

A gating circuit responsive to first and second complementary input signals from a first signal source and third and fourth complementary input signals from a second signal source for generating first and second complementary output signals, said circuit comprising: first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second input signals, respectively, and collector terminals providing said first and second output signals, respectively; third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second input signals, respectively, and collector terminals coupled to the collector terminals of the second and first switching transistors, respectively; fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said third and fourth input signals, respectively, and collector terminals coupled to the intercoupled emitter terminals of the first and second switching transistors and the intercoupled emitter terminals of the third and fourth switching transistors, respectively; means coupled to the emitter terminals of the fifth and sixth switching transistors for generating a predetermined bias current; and first and second load means coupled between a power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal.

Claim 8

A gating circuit responsive to first and second complementary input signals from a first signal source and third and fourth complementary input signals from a second signal source for generating first and second complementary output signals, said circuit comprising: first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second input signals, respectively, and collector terminals providing said first and second output signals, respectively; third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second input signals, respectively, and collector terminals coupled to the collector terminals of the second and first switching transistors, respectively; fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said third and fourth input signals, respectively, and collector terminals coupled to the intercoupled emitter terminals of the first and second switching transistors and the intercoupled emitter terminals of the third and fourth switching transistors, respectively; means coupled to the emitter terminals of the fifth and sixth switching transistors for generating a predetermined bias current; and first and second load means coupled between a power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal.

Claim 9

The circuit according to claim 5, wherein said bias current generating means includes means for varying the generated bias current in response to a control signal from a control signal source.

Claim 10

A gating circuit having first and second complementary output signals for storing first and second complementary input signals from a first signal source in response to first and second complementary strobe signals from a second signal source, said circuit comprising: first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said second and first output signals, respectively, and collector terminals providing said first and second output signals, respectively; third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second input signals, respectively, and collector terminals coupled to the collector terminals of the first and second switching transistors, respectively; fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second strobe signals, respectively, and collector terminals coupled to the intercoupled emitter terminals of the third and fourth switching transistors and the intercoupled emitter terminals of the first and second switching transistors, respectively; means coupled to the emitter terminals of the fifth and sixth switching transistorss for generating a predetermined bias current; and first and second load means coupled between a power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal.

Claim 11

A gating circuit having first and second complementary output signals for storing first and second complementary input signals from a first signal source in response to first and second complementary strobe signals from a second signal source, said circuit comprising: first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said second and first output signals, respectively, and collector terminals providing said first and second output signals, respectively; third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second input signals, respectively, and collector terminals coupled to the collector terminals of the first and second switching transistors, respectively; fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second strobe signals, respectively, and collector terminals coupled to the intercoupled emitter terminals of the third and fourth switching transistors and the intercoupled emitter terminals of the first and second switching transistors, respectively; means coupled to the emitter terminals of the fifth and sixth switching transistorss for generating a predetermined bias current; and first and second load means coupled between a power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal.

Claim 12

The circuit according to claim 7, wherein said bias current generating means includes for varying the generated bias current in response to a control signal from a control signal source.

Claim 13

A flip-flop circuit having first and second complementary flip-flop output signals for storing first and second complementary flip-flop input signals from a first signal source in response to first and second complementary clock signals from a second signal source, said circuit comprising: (a) master and slave circuit means, each having first and second complementary input signals and first and second complementary output signals, the first and second slave output signals providing the first and second flip-flop output signals, respectively, the first and second master input signals being coupled to the first and second flip-flop input signals, respectively, and the first and second slave input signals being coupled to the second and first master output signals, respectively; (b) said master circuit means comprising: (i) first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said second and first master output signals, respectively, and collector terminals providing said first and second master output signals, respectively; (ii) third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second master input signals, respectively, and collector terminals coupled to the collector terminals of the first and second switching transistors, respectively; (iii) fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second clock signals for said slave circuit means and to said second and first clock signals for said master circuit means, respectively, and collector terminals coupled to the intercoupled emitter terminals of the third and fourth switching transistors and the intercoupled emitter terminals of the first and second switching transistors, respectively; and (iv) first and second load means coupled between a power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal; (c) said slave circuit means comprising: (i) first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said second and first slave output signals, respectively, and collector terminals providing said first and second slave output signals, respectively; (ii) third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second slave input signals, respectively, and collector terminals coupled to the collector terminals of the first and second switching transistors, respectively; (iii) fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second clock signals for said slave circuit means and to said second and first clock signals for said master circuit means, respectively, and collector terminals coupled to the intercoupled emitter terminals of the third and fourth switching transistors and the intercoupled emitter terminals of the first and second switching transistors, respectively; and (iv) first and second load means coupled between the power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal; and (d) means coupled to the emitter terminals of the fifth and sixth switching transistors in the master and slave circuit means for generating a predetermined bias current.

Claim 14

A flip-flop circuit having first and second complementary flip-flop output signals for storing first and second complementary flip-flop input signals from a first signal source in response to first and second complementary clock signals from a second signal source, said circuit comprising: (a) master and slave circuit means, each having first and second complementary input signals and first and second complementary output signals, the first and second slave output signals providing the first and second flip-flop output signals, respectively, the first and second master input signals being coupled to the first and second flip-flop input signals, respectively, and the first and second slave input signals being coupled to the second and first master output signals, respectively; (b) said master circuit means comprising: (i) first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said second and first master output signals, respectively, and collector terminals providing said first and second master output signals, respectively; (ii) third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second master input signals, respectively, and collector terminals coupled to the collector terminals of the first and second switching transistors, respectively; (iii) fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second clock signals for said slave circuit means and to said second and first clock signals for said master circuit means, respectively, and collector terminals coupled to the intercoupled emitter terminals of the third and fourth switching transistors and the intercoupled emitter terminals of the first and second switching transistors, respectively; and (iv) first and second load means coupled between a power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal; (c) said slave circuit means comprising: (i) first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said second and first slave output signals, respectively, and collector terminals providing said first and second slave output signals, respectively; (ii) third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second slave input signals, respectively, and collector terminals coupled to the collector terminals of the first and second switching transistors, respectively; (iii) fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second clock signals for said slave circuit means and to said second and first clock signals for said master circuit means, respectively, and collector terminals coupled to the intercoupled emitter terminals of the third and fourth switching transistors and the intercoupled emitter terminals of the first and second switching transistors, respectively; and (iv) first and second load means coupled between the power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal; and (d) means coupled to the emitter terminals of the fifth and sixth switching transistors in the master and slave circuit means for generating a predetermined bias current.

Claim 15

The circuit according to claim 9, wherein said bias current generating means includes means for varying the generated bias current in response to a control signal from a control signal source.

Claim 16

A dual modulus dividing circuit for dividing first and second complementary clock signals from a clock signal source to generate first and second complementary output signals related to the first and second clock signals by a first modulus and a second modulus in response to the first and second complementary modulus control signals from a control signal source, said dividing circuit comprising: (a) first and second flip-flop circuits each including master and slave circuit means and each having first and second complementary flip-flop output signals for storing first and second complementary flip-flop input signals in response to the first and second complementary clock signals, the first and second output signals of the first flip-flop circuit being coupled to the first and second input signals of the second flip-flop circuit, respectively, the first and second output signals of the second flip-flop circuit coupled to the second and first input signals of the first flip-flop circuit, respectively, and said master and slave circuit means each having first and second complementary input signals and first and second complementary output signals, the first and second slave output signals providing the first and second flip-flop output signals, respectively, the first and second master input signals being coupled to the first and second flip-flop input signals, respectively, and the first and second slave input signals being coupled to the first and second master output signals; (b) said master circuit means comprising: (i) first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said second and first master output signals, respectively, and collector terminals providing said first and second master output signals, respectively; (ii) third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second master input signals, respectively, and collector terminals coupled to the collector terminals of the first and second switching transistors, respectively; (iii) fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second clock signals for said slave circuit means and to said second and first clock signals for said master circuit means, respectively, and collector terminals coupled to the intercoupled emitter terminals of the third and fourth switching transistors and the intercoupled emitter terminals of the first and second switching transistors, respectively; and (iv) first and second load means coupled between a power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal; (c) said slave circuit means comprising: (i) first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said second and first slave output signals, respectively, and collector terminals providing said first and second slave output signals, respectively; (ii) third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second slave input signals, respectively, and collector terminals coupled to the collector terminals of the first and second switching transistors, respectively; (iii) fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second clock signals for said slave circuit means and to said second and first clock signals for said master circuit means, respectively, and collector terminals coupled to the intercoupled emitter terminals of the third and fourth switching transistors and the intercoupled emitter terminals of the first and second switching transistors, respectively; and (iv) first and second load means coupled between the power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal; and (d) means coupled to the emitter terminals of the fifth and sixth switching transistors in the master and slave circuit means in the first and second flip-flop circuits for generating a predetermined bias current; and (e) a modulus control circuit coupled to a modulus control signal from a control signal source and being interposed between the intercoupled emitter terminals of the third and fourth switching transistors in the master circuit means in the first flip-flop circuit and the collector terminal of the fifth switching transistor in the master circuit means in the first flip-flop circuit, said modulus control circuit including seventh, eighth and ninth switching transistors each having base terminals, collector terminals and emitter terminals, the emitter terminals being intercoupled to one another, the base terminals of the seventh and eighth switching transistors being coupled to the first and second slave output signals in the first flip-flop circuit, the base terminal of the ninth switching transistor being coupled to the modulus control signal, the collector terminals of the seventh and ninth switching transistors being coupled to the intercoupled emitter terminals of the third and fourth switching transistors in the master circuit means in the first flip-flop circuit, the collector terminal of the eighth switching transistor being coupled to the collector terminal of the fourth switching transistor in the master circuit means in the first flip-flop circuit, and the emitter terminals of the seventh, eighth and ninth switching transistors being coupled to the collector terminal of the fifth switching transistor in the master circuit means in the first flip-flop circuit.

Claim 17

A dual modulus dividing circuit for dividing first and second complementary clock signals from a clock signal source to generate first and second complementary output signals related to the first and second clock signals by a first modulus and a second modulus in response to the first and second complementary modulus control signals from a control signal source, said dividing circuit comprising: (a) first and second flip-flop circuits each including master and slave circuit means and each having first and second complementary flip-flop output signals for storing first and second complementary flip-flop input signals in response to the first and second complementary clock signals, the first and second output signals of the first flip-flop circuit being coupled to the first and second input signals of the second flip-flop circuit, respectively, the first and second output signals of the second flip-flop circuit coupled to the second and first input signals of the first flip-flop circuit, respectively, and said master and slave circuit means each having first and second complementary input signals and first and second complementary output signals, the first and second slave output signals providing the first and second flip-flop output signals, respectively, the first and second master input signals being coupled to the first and second flip-flop input signals, respectively, and the first and second slave input signals being coupled to the first and second master output signals; (b) said master circuit means comprising: (i) first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said second and first master output signals, respectively, and collector terminals providing said first and second master output signals, respectively; (ii) third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second master input signals, respectively, and collector terminals coupled to the collector terminals of the first and second switching transistors, respectively; (iii) fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second clock signals for said slave circuit means and to said second and first clock signals for said master circuit means, respectively, and collector terminals coupled to the intercoupled emitter terminals of the third and fourth switching transistors and the intercoupled emitter terminals of the first and second switching transistors, respectively; and (iv) first and second load means coupled between a power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal; (c) said slave circuit means comprising: (i) first and second switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said second and first slave output signals, respectively, and collector terminals providing said first and second slave output signals, respectively; (ii) third and fourth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second slave input signals, respectively, and collector terminals coupled to the collector terminals of the first and second switching transistors, respectively; (iii) fifth and sixth switching transistors each having emitter terminals intercoupled to one another, base terminals coupled to said first and second clock signals for said slave circuit means and to said second and first clock signals for said master circuit means, respectively, and collector terminals coupled to the intercoupled emitter terminals of the third and fourth switching transistors and the intercoupled emitter terminals of the first and second switching transistors, respectively; and (iv) first and second load means coupled between the power source and collector terminals of the first and second switching transistors, respectively, said first and second load means each being comprised of at least two series coupled, forward biased transistors interconnected to one another for continuously conducting current from said power source and each having an emitter terminal, a base terminal and a collector terminal connected to the base terminal; and (d) means coupled to the emitter terminals of the fifth and sixth switching transistors in the master and slave circuit means in the first and second flip-flop circuits for generating a predetermined bias current; and (e) a modulus control circuit coupled to a modulus control signal from a control signal source and being interposed between the intercoupled emitter terminals of the third and fourth switching transistors in the master circuit means in the first flip-flop circuit and the collector terminal of the fifth switching transistor in the master circuit means in the first flip-flop circuit, said modulus control circuit including seventh, eighth and ninth switching transistors each having base terminals, collector terminals and emitter terminals, the emitter terminals being intercoupled to one another, the base terminals of the seventh and eighth switching transistors being coupled to the first and second slave output signals in the first flip-flop circuit, the base terminal of the ninth switching transistor being coupled to the modulus control signal, the collector terminals of the seventh and ninth switching transistors being coupled to the intercoupled emitter terminals of the third and fourth switching transistors in the master circuit means in the first flip-flop circuit, the collector terminal of the eighth switching transistor being coupled to the collector terminal of the fourth switching transistor in the master circuit means in the first flip-flop circuit, and the emitter terminals of the seventh, eighth and ninth switching transistors being coupled to the collector terminal of the fifth switching transistor in the master circuit means in the first flip-flop circuit.

Claim 18

The dividing circuit according to claim 11, wherein siad bias current generating means includes means for varying the generated bias current in response to a control signal from a control signal source.