Schottky loaded emitter coupled memory cell for random access memory

Claim 1

A memory cell for non-destructive addressing and readout, said memory cell comprising: a pair of sense/write lines also serving as one set of decode lines, a voltage line unconnected to said pair of sense/write lines and serving as the other decode line orthogonally related to said one set of decode lines, a bistable circuit including first and second transistors having respective collector, base and emitter electrodes connected in cross-coupled relationship, each of said emitter electrodes for said first and second transistors including emitter pairs comprising an access/sense emitter and a store emitter, the store emitters of each emitter pair being connected in common, and the access/sense emitters of each emitter pair being respectively connected to the one of the pair of sense/write lines corresponding thereto, a store current source connected to said commonly coupled store emitters for maintaining a standby cell current through said first and second transistors via the store emitters thereof, first and second Schottky diodes respectively connected to the collector electrodes of said first and second transistors at one end thereof and to said voltage line at the other end thereof, the base electrode of said first transistor being connected to a junction point between said second Schottky diode and said collector electrode of said second transistor, and the base electrode of said second transistor being connected to a junction point between said first Schottky diode and said collector electrode of said first transistor.