US4316151A
Expired / Lapsed
US
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Phase locked loop frequency synthesizer using multiple dual modulus prescalers
Assignee: Motorola Solutions Inc
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Filing: 1980-02-13
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Granted: 1982-02-16
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Expires: 2000-02-13
Abstract
Abstract An improved frequency synthesizer suitable for use in mobile and portable radio applications using multiple dual modulus prescalers to achieve high frequency operation and low current drain. A first high speed prescaler of limited size is used in conjunction with a second prescaler to avoid the use of one large high speed prescaler to attain high frequency operation. Consequently, the frequency synthesizer can be constructed using only a minimum amount of high speed, high current drain logic thereby reducing costs and power consumption.
Inventors
- 👤 William J. Ooms
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 00:21
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/193; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/667
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
305 words
An improved frequency synthesizer comprising: (a) a reference signal source for generating a reference signal; (b) a phase comparator, having a first input coupled to the signal source, a second input and an output, for producing at the output a control signal representative of the phase difference of signals received at the first and second input; (c) a signal controlled oscillator for producing an oscillator signal of frequency f at its output in response to the phase comparator control signal; and (d) divider means for frequency dividing the controlled oscillator signal by a divisor N T and applying the divided signal to the second input of the phase comparator including, first prescaler means for frequency dividing the controlled oscillator signal by one of two predetermined integer divisors M and M' and producing a divided output signal, means for counting the output signals from the first prescaler and producing an output signal when C signals have been counted when said counting means is enabled, second prescaling means for frequency dividing the output signal of the first prescaling means by one of two predetermined integer divisors P and P', and producing a divided output signal, frequency dividing means, coupled to the second prescaler, for frequency dividing the output signal of the second prescaler to produce an output signal of frequency f/N T at an output, and means for controlling the first prescaler and the counting means such that the counting means is enabled when the first prescaler is dividing the input signal by M' and such that the first prescaler is actuated from its M' divisor to its M divisor in response to the output signal from the counter means, and such that the first prescaler is actuated from its M divisor to its M' divisor in response to the output signal of the frequency dividing means.
Claim 2
Dependent Claim
305 words
An improved frequency synthesizer comprising: (a) a reference signal source for generating a reference signal; (b) a phase comparator, having a first input coupled to the signal source, a second input and an output, for producing at the output a control signal representative of the phase difference of signals received at the first and second input; (c) a signal controlled oscillator for producing an oscillator signal of frequency f at its output in response to the phase comparator control signal; and (d) divider means for frequency dividing the controlled oscillator signal by a divisor N T and applying the divided signal to the second input of the phase comparator including, first prescaler means for frequency dividing the controlled oscillator signal by one of two predetermined integer divisors M and M' and producing a divided output signal, means for counting the output signals from the first prescaler and producing an output signal when C signals have been counted when said counting means is enabled, second prescaling means for frequency dividing the output signal of the first prescaling means by one of two predetermined integer divisors P and P', and producing a divided output signal, frequency dividing means, coupled to the second prescaler, for frequency dividing the output signal of the second prescaler to produce an output signal of frequency f/N T at an output, and means for controlling the first prescaler and the counting means such that the counting means is enabled when the first prescaler is dividing the input signal by M' and such that the first prescaler is actuated from its M' divisor to its M divisor in response to the output signal from the counter means, and such that the first prescaler is actuated from its M divisor to its M' divisor in response to the output signal of the frequency dividing means.
Claim 3
Dependent Claim
13 words
The improved frequency synthesizer of claim 1 wherein the counting means is programmable.
Claim 4
Dependent Claim
39 words
The improved frequency synthesizer of claims 1 or 2 wherein the frequency dividing means is programmable such that divisor from the output of the first prescaler to the output of the dividing means is programmable in increments of one.
Claim 5
Dependent Claim
147 words
The improved high frequency synthesizer of claims 1 or 2 wherein the frequency dividing means comprises: means for frequency dividing the second prescaler divided output signal by a divisor A; means for frequency dividing the second prescaler divided output signal by a divisor B; logic means for controlling the second prescaling means and the dividing means so that the second prescaler divided output signal is alternately frequency divided by A and B, and the dividing means is preset while the division by B is occurring and the B dividing means is preset while the division by A is occurring, said logic means including means for actuating the second prescaling means from its P' divisor to its P divisor upon transition from the A divisor to the B divisor and from its P divisor to its P' divisor upon transition from the B divisor to the A divisor.
Claim 6
Dependent Claim
50 words
The improved frequency synthesizer of claim 1, or 2 further comprising: means, coupled to the phase comparator output and to the signal controlled oscillator, for processing the control signal from the phase comparator to produce a filtered control signal and for applying the filtered control signal to the controlled oscillator.
Claim 7
Dependent Claim
209 words
A high speed frequency divider responsive to a source of input signals of frequency f, comprising: first prescaling means for frequency dividing the input signal by one of two predetermined integer divisors M and M' and producing a divided output signal; means for counting the output signals from the first prescaler and producing an output signal when C signals have been counted when the counting means is enabled; second prescaling means for frequency dividing the output signal of the first prescaling means by one of two predetermined integer divisors P and P' and producing a divided output signal; frequency dividing means, coupled to the second prescaler, for frequency dividing the output signal of the second prescaler to produce an output signal of frequency F divided by N; and means for controlling the first prescaler and the counting means such that the counting means is enabled when the first prescaler is dividing the input signal by M', and such that the first prescaler is actuated from its M' divisor to its M divisor in response to the output signal from the counter means, and such that the first prescaler is actuated from its M divisor to its M' divisor in response to the output signal from the frequency dividing means.
Claim 8
Dependent Claim
209 words
A high speed frequency divider responsive to a source of input signals of frequency f, comprising: first prescaling means for frequency dividing the input signal by one of two predetermined integer divisors M and M' and producing a divided output signal; means for counting the output signals from the first prescaler and producing an output signal when C signals have been counted when the counting means is enabled; second prescaling means for frequency dividing the output signal of the first prescaling means by one of two predetermined integer divisors P and P' and producing a divided output signal; frequency dividing means, coupled to the second prescaler, for frequency dividing the output signal of the second prescaler to produce an output signal of frequency F divided by N; and means for controlling the first prescaler and the counting means such that the counting means is enabled when the first prescaler is dividing the input signal by M', and such that the first prescaler is actuated from its M' divisor to its M divisor in response to the output signal from the counter means, and such that the first prescaler is actuated from its M divisor to its M' divisor in response to the output signal from the frequency dividing means.
Claim 9
Dependent Claim
14 words
The high speed frequency divider of claim 6, wherein the counting means is programmable.
Claim 10
Dependent Claim
148 words
The high speed frequency divider of claim 6 or 7, wherein the frequency dividing means further comprises: means for frequency dividing the second prescaler divided output signal by divisor A; means for frequency dividing the second prescaler divided output signal by divisor B; logic means for controlling the second prescaling means and the dividing means so that the second prescaler divided output signal is alternately frequency divided by A and B, and the A dividing means is preset while the division by B is occurring and the B dividing means is preset while the division by A is occurring; said logic means including means for actuating the second prescaling means from its P' divisor to its P divisor upon the transition from the A divisor to the B divisor and from its P divisor to its P' divisor upon transition from the B divisor to the A divisor.
Claim 11
Dependent Claim
20 words
A high speed frequency divider of claim 8, wherein the A divider means and the B divider means are programmable.
References Cited (Backward Citations)
US3811092A
Cited
US3805192A
Cited
US3849635A
Cited
US3976946A
Cited
US3959737A
Cited
US4033633A
Cited
US4121162A
Cited
US4053739A
Cited
US4184068A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-02-15 | 1985-08-17 | 1986-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-02-15 | 1989-08-17 | 1990-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-02-15 | 1993-08-17 | 1994-02-16 | $7700.00 | Window Closed / Lapsed |