Variable-ratio electronic counter-divider

Claim 2

Frequency divider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of the second scale being connected to the pulse output of the first scale, wherein the first scale has a control input and is set so that its division ratio shifts in whole units under the action of control signals applied to its control input, the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal and means for enabling the control signal for a predetermined number of the counts displayed by the second scale.

Claim 3

Frequency divider in accordance with claim 1, characterised in that the second scale includes a decimal counter and a binary amplitude comparator which compares the count of said counter with said predetermined number.

Claim 4

Frequency divider in accordance with claim 1, characterised in that the second scale includes a bit rate multiplier.

Claim 5

Frequency divider in accordance with claim 1, characterized in that the second scale moreover includes means for comparing the count of the fixed-capacity counter with at least one instruction number to enable at least one control signal and thus shift the division ratio by at least one unit.

Claim 6

Frequency divider in accordance with claim 4, characterised in that at least one of the instruction numbers is variable.

Claim 7

Frequency divider in accordance with claim 4, characterised in that, the counter being decimal, a first instruction number varies between 0 and 10n -1, a second instruction number being fixed and less than 10n -1.

Claim 8

Counter-divider in accordance with claim 4, wherein said means are binary amplitude comparators associated with a logical circuit.

Claim 9

Frequency divider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of the second scale being connected to the pulse output of the first scale, wherein the first scale has a control input and is set so that its division ratio shifts in whole units under the action of control signals applied to its control input, the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal and means for enabling the control signal for a predetermined number of the counts displayed by the second scale, the first scale including a number of J K flip-flops at least equal to the value which its division raTio assumes when the control signal is not enabled, the said flip-flops having clock impulse driven in synchronism by the frequency to be divided, the said flip-flops further having J and K inputs and Q and Q outputs, the Q output of the first flip-flop driving the J inputs of the other flip-flops and the pulse input of the second scale, the Q output of each of said other flip-flops driving the K input of the next flip-flop down with the exception of the first, the Q output of the second flip-flop driving the J input of the first, the K inputs of the first and last flip-flops being connected to a One logical level, the last flip-flop having a further input Jx to which said control signal is applied.

Claim 10

Frequency divider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of the second scale being connected to the pulse output of the first scale, wherein the first scale has a control input and is set so that its division ratio shifts in whole units under the action of control signals applied to its control input, the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal and means for enabling the control signal for a predetermined number of the counts displayed by the second scale, the first scale including a number of J K flip-flops at least equal to the value which its division raTio assumes when the control signal is not enabled, the said flip-flops having clock impulse driven in synchronism by the frequency to be divided, the said flip-flops further having J and K inputs and Q and Q outputs, the Q output of the first flip-flop driving the J inputs of the other flip-flops and the pulse input of the second scale, the Q output of each of said other flip-flops driving the K input of the next flip-flop down with the exception of the first, the Q output of the second flip-flop driving the J input of the first, the K inputs of the first and last flip-flops being connected to a One logical level, the last flip-flop having a further input Jx to which said control signal is applied.

Claim 11

Frequency divider in accordance with claim 8, characterised in that the first scale comprises means for varying its division ratio by grounding some of the inputs of the flip-flops which it comprises.

Claim 12

Frequency divider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of the second scale being connected to the pulse output of the first scale, wherein the first scale has a control input and is set so that its division ratio shifts in whole units under the action of control signals applied to its control input, the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal and means for enabling the control signal for a predetermined number of the counts displayed by the second scale, the second scale including a decimal counter having first and second outputs, means for generating a One logical level respectively at said first output when the count of the decimal counter coincides with said predetermined number and at a second output when the said count coincides with the zero value, and a J K flip-flop supplying said control signal and having K and J inputs connected to said first and second outputs respectively.

Claim 13

Frequency divider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of the second scale being connected to the pulse output of the first scale, wherein the first scale has a control input and is set so that its division ratio shifts in whole units under the action of control signals applied to its control input, the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal and means for enabling the control signal for a predetermined number of the counts displayed by the second scale, the second scale including a decimal counter having first and second outputs, means for generating a One logical level respectively at said first output when the count of the decimal counter coincides with said predetermined number and at a second output when the said count coincides with the zero value, and a J K flip-flop supplying said control signal and having K and J inputs connected to said first and second outputs respectively.

Claim 14

Frequency divider in accordance with claim 10, wherein said first output is connected on the one hand to the K input of the flip-flop and on the onther hand, via a logical inverter, to a first input of an AND gate having first and second inputs, said second output being directly connected to the second input of the AND gate, said AND gate having an output connected at the J input of the said flip-flop.

Claim 15

Frequency devider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of the second scale being connected to the pulse output of the first scale, wherein the first scale has a control input and is set so that its division ratio shifts in whole units under the action of control signals applied to its control input, the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal and means for enabling the control signal for a predetermined number of the counts displayed by the second scale, the first division scale comprising a shift register of the type having a mode control input which, according to whether or not it is enabled, makes it possible to obtain the transfer in parallel of information from the parallel inputs to the corresponding parallel outputs thereof, or to obtain the gradual transfer of the information from one parallel output thereof to the following ones, one of the parallel outputs of said shift register being connected to the fixed-capacity counter and to the said mode control input and means for comparing the count of the fixed-capacity counter with at least one instruction number to enable at least one control signal and thus shift the division ratio by at least one unit, the said comparing means being connected to some of the parallel inputs.

Claim 16

Frequency devider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of the second scale being connected to the pulse output of the first scale, wherein the first scale has a control input and is set so that its division ratio shifts in whole units under the action of control signals applied to its control input, the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal and means for enabling the control signal for a predetermined number of the counts displayed by the second scale, the first division scale comprising a shift register of the type having a mode control input which, according to whether or not it is enabled, makes it possible to obtain the transfer in parallel of information from the parallel inputs to the corresponding parallel outputs thereof, or to obtain the gradual transfer of the information from one parallel output thereof to the following ones, one of the parallel outputs of said shift register being connected to the fixed-capacity counter and to the said mode control input and means for comparing the count of the fixed-capacity counter with at least one instruction number to enable at least one control signal and thus shift the division ratio by at least one unit, the said comparing means being connected to some of the parallel inputs.

Claim 17

Frequency divider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of thE second scale being connected to the pulse output of the first scale, wherein the first scale has a control input and is set so that its division ratio shifts by one unit under the action of control signals applied to its control input, the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal, the second scale further including a binary amplitude comparator comparing the count of said fixed-capacity counter with an instruction number to generate said control signals, the fixed-capacity counter comprising a scale-of-N followed by a scale-of-two, and the binary amplitude comparator being set to compare the binary number expressed by the logical levels of the parallel outputs of the scale-of-N with a binary number n - a/2, n being the instruction number and ''''a'''' a nil value when n is even, and a value equal to 1 when is odd, and means, associated with the comparator, for enabling or not enabling the output signal of the comparator, according to the parity of n, said means only acting for N of the counts of the fixed-capacity counter.

Claim 18

Frequency divider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of thE second scale being connected to the pulse output of the first scale, wherein the first scale has a control input and is set so that its division ratio shifts by one unit under the action of control signals applied to its control input, the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal, the second scale further including a binary amplitude comparator comparing the count of said fixed-capacity counter with an instruction number to generate said control signals, the fixed-capacity counter comprising a scale-of-N followed by a scale-of-two, and the binary amplitude comparator being set to compare the binary number expressed by the logical levels of the parallel outputs of the scale-of-N with a binary number n - a/2, n being the instruction number and ''''a'''' a nil value when n is even, and a value equal to 1 when is odd, and means, associated with the comparator, for enabling or not enabling the output signal of the comparator, according to the parity of n, said means only acting for N of the counts of the fixed-capacity counter.

Claim 19

Frequency divider in accordance with claim 13, characterised by a comparator comprising K couples of inputs with respectively decreasing priorities, the (K - 2) first inputs on one side of the comparator receiving logical levels which define the respective binary digits of the instruction number, with the exception of the binary units digit, while the next input receives a predetermined logical level, the (K - 1) first inputs of the other side of the comparator being connected to the respective outputs of the fixed-capacity counter, the last couple of inputs of the comparator being connected to means for enabling or not enabling, according to whether the instruction number is even or odd, those of the inputs of said couple which will enable the output signal of the comparator for N of the counts of the fixed-capacity counter.

Claim 20

Frequency-divider in accordance with claim 14, characterised by a decimal counter comprising a scale-of-five followed by a scale-of-two, and by a binary comparator having a first couple of inputs which respectively receive the 1 weight output of the counter and the 8 code of the instruction number, a second couple of inputs which respectively receive the 2 weight output of the counter and the 4 code of the instruction number, a third couple of inputs which respectively receive the 1 weight output of the counter and the 2 code of the instruction number, a fourth couple of inputs which respectively receive the 5 weight output of the counter and a Zero logical level, and a fifth couple of inputs respectively connected to the 1 code of the instruction number, directly and via a logical inverter, said couples of inputs having priorities decreasing in the order in which they are enumerated.